![](http://datasheet.mmic.net.cn/370000/L6256_datasheet_16703406/L6256_15.png)
VCM Control Register
Bit Function
VCM DAC attenuation
switches - 3 bits (5)d
1.5:1
2:1
4:1
Thermal Limit
Register Park
Address: 0001
Init State
Mnemonic
Bit #
R/W
Read 1 indicates:
ATT0
ATT1
ATT2
TH_LIM
RPARK
0
1
2
3
4
xxx
xxx
xxx
0
On
W
W
W
N/A
N/A
N/A
Read
R/W
Th Limit
Park Delay is
Occuring (1)
Driver Saturated (2)
Tristated (3)
Current
Outside
Window (4)
Saturate Seek
VCM Tristate
VCM loopback (read)
SAT_SK
VCM_3S
VCM_LP
5
6
7
0
R/W
W
Read
xxx
xxx
Done Disable (write) (6)
DONE_DIS
7
Write
(1) Register park will not cause a brake to occur. The register park bit will also go low during a register brake, indicating to the firmware that
the brake sequence has been initiated.
(2) Saturated seek bit, when 1, will cause the VCM drivers to saturate, with the polarity of the sign bit in the VCM DAC register. A read of this
bit indicates that the commanded current differs from the actual current (output of the saturation comparator). NOTE: this is not just an
echo of the state of the written bit, but actually represents the true status of the VCM current loop.
(3) This bit tristates but leaves internal circuitry active for external test (ST), or is unused (Unitrode). The DONE_DIS bit has been moved
(see note 4).
(4) VCM loopback is optional. Use the saturated seek bit for test purposes. The DONE_DIS bit is used to end the park timer cycle, which
may be necessary if the chip is ever put into run mode at low speed.
(5) Exact attenuation ratios may vary slightly between manufacturers. See data sheets. Attenuators are now gated by ATT_EN, which is lo-
cated in S2 in the address space of the VCM register. IfATT_EN is high, the attenuation is set by the value in this register. If ATT_EN is
low, full gain (no attenuation) is selected. This allows rapid switching between low and high gain with the same write packet as that used
to write to the DAC.
(6) DONE_DIS MUST be cleared when entering run mode, or the park timer will stay off. This bit should never be used except during error
recovery.
Commutation Preload Register (CPR-Write only)
Bit Function
Spindle ABC low enb (3 bits)
A low enb
B low enb
C low enb
Spindle ABC high enb (3 bits)
A high enb
B high enb
C high enb
Spare
Spare
Address: 0011
Bit Address
initial state: XXX (2)
Bit 0
Bit 1
Bit 2
initial state: XXX (2)
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
NOTES:
- All bits become valid only on a rising SP_CLK edge, except CHB_ENB.
- Spindle high bits override low bits. Transition from low to high and vice versa are interlocked against simultaneous enables or momentary
shootthrough.
- An all 1’s pattern in this register, bits 0 through 5, causes the internal Commutation Counter to begin operation on the next SPIN_CLK input
edge. Any other pattern causes the spindle Commutation Counter to reset (BC\ state).
(1) CHB_ENB, when high (the POR and default condition), allows the back EMF chop blanking comparator to disable spindle PWM off peri-
ods during the A phase negative crossing (see back EMF detection section). Initial state varies between vendors.
(2) the 6 bits which determine the spindle driver must be set to all 1’s before entering run mode or the CCTR will not run.
L6256
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