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參數(shù)資料
| 型號： | L6256 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 12V COMBO |
| 中文描述： | 12V的組合 |
| 文件頁數(shù)： | 10/28頁 |
| 文件大?。?/td> | 258K |
| 代理商： | L6256 |
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Protocol (general):
This protocol is part of a multiple chip protocol
which affects several different Western Digital
chip specifications. Changes to this protocol will
affect several vendors.
Specifications for this chip conform to the timing
specification
The serial protocol used to communicate with the
chip is based on a fixed length 2 byte write or 3
byte read cycle (packets). Each packet sent to
the chip is qualified by Dolphin chi select and by
the address section of the first byte sent to the
chip (bits transferred on clock cycles 2 through 4).
The R/W bit determines packet length and bus di-
rection.
At the end of the 16th bit (write) the data is trans-
ferred to the appropriate registers.
At the end of the 8th (read) bit, the internally ad-
dressed registers is ready to be placed on the se-
rial bus. A dead bit is provided in all cases as the
first bit read back from the Dolphin, to allow inter-
nal propagation delays and to provide for use of
the clock to gate data into the internal shift regis-
ter. At high data rates the processor has to insert
some time in order to turn the bus around from
write to read mode.
Multiple packets can be sent back to back without
a dead space in between when other chips are
addressed (except for the specified clock cycles
inserted by the processor hardware). The chip is
able to decode this case.
At high data rates, a dead space of at least 1
clock cycle must be allowed in between bytes of
the packet for propagation delays internally.
t
fall
V
CC
V
min
V
tcap
POR\
V
ccmin
V
tcap
V
cth
Internal POR
t
pmin
t
stretch
V
min
V
min
V
lw
V
porint
D97IN587
Figure 4:
Power On Reset Waveforms and Timing
Thermal Shutdown Section
Symbol
T
Hlimit
T
hhyst
T
hwarn
Parameter
Value
Unit
°C
°C
°C
Thermal Shutdown Die Temperature (1)
Thermal Shutdown Hysteresis (1)
Thermal Warning (1)
15
±
5 above Thwarn
10
145
±
15
(1) Guaranteed by design
SERIAL PORT SECTION
General Specification
Data rate
Clock Byte Synchronization
Max load to external parts
Max external load
Max bus load capacitance
Output Drive Structure
6 to 12.5MHz
internal
15pF
5mA or 1.2K pullup
60pF
3 state, active high and
low (not open drain)
7MHz (see timing
section) (1)
none
Min Speed without dead bit
Internal pullup resistor
(1) Clock duty cycle of 40% to 60%
L6256
10/28
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| L6258 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:PWM controlled high current DMOS universal motor driver |
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| L6258E_07 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:PWM controlled high current DMOS universal motor driver |
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