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參數(shù)資料
| 型號： | L6256 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 12V COMBO |
| 中文描述： | 12V的組合 |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 258K |
| 代理商： | L6256 |
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Format for write to the Dolphin DAC:
Write:
10 Bits
to DAC
dead
cycle
1 cycle
min
1 cycle
min
Bit
R/W-
S0
S1
ATT_ENB
(*)
D3
A0 (1)
A1
D8
D9
D0
D1
D2
D4
D5
D6
D7
(*) indicates a change in the specification.
If the ATT_ENB is a 1, then the DAC output attenuation will be enabled, and the attenuation will be what-
ever has been previously written in the VCM control register (this may include no attenuation at all). If the
bit is 0, the attenuator is disabled and high gain is forced.
Format for write to all other Dolphin registers:
Write:
10 Bits
to DAC
dead
cycle
1 cycle
min
1 cycle
min
Bit
R/W-
S0
S1
S2
A0 (1)
A1
D8
D9
D0
D1
D2
D3
D4
D5
D6
D7
Format for write to the chips other than the 12V combo:
Write:
1Byte
dead
cycle
none (1)
none (1)
Bit
R/W-
D0
S0
D1
S1
D2
S2
D3
A0
D4
A1
D5
A2
D6
A3
D7
(1) There may not be a dead cycle between write addresses and their data bits when data is addressed to another chip on the serial port.
NOTE: All registers are accessible during POR to allow for in circuit testing. Appropriate functional chip changes may be occurring during the
reset.
Serial Port Timing Specifications
Parameter
T
setup
T
hold
From/To
V
dh
or V
dl
to V
ch
SCLK high to
invalid SDIO, read
valid SDIO to
SCLK high
SCLK high to
invalid SDIO, write
CSELB low to
first falling clock
last rising clock to
CSELB high
Min.
45
0
Typ.
Max.
Units
ns
ns
T
suw
10
ns
T
holdw
5
ns
T
csck
133
ns (1)
T
cschigh
133
ns (1)
(1) CSELB specifications apply to both read and write operations. Timing is only shown in the read operation digram.
Minimum Timing for non-dead bit operation:
Timing Parameter
T
sclklow
T
sclkhigh
Ref Point
SCLK Vdl to Vdh
SCLK Vdh to Vdl
Min.
56
56
Typ.
Max.
Units
ns
ns
Threshold voltage for SDIO, internal to Dolphin:
V
th
SDIO Logic
Threshold
1.0
1.2
1.7
V
L6256
13/28
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