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參數(shù)資料
| 型號(hào)： | L6256 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 12V COMBO |
| 中文描述： | 12V的組合 |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 258K |
| 代理商： | L6256 |
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Table of Address Values
S0, S1, S2 always 1 - any other value indicates a
packet for use by another chip.
S2 may be used only as part of the VCM register
address, as ATT_EN.
Register
A0-3
11xx
0111
0001
0011
R/W
VCM DAC
Aux Control Register
VCM Control Register
Commutation Preload
Register (CPR)
Test Register (*)
Status Register
Write Only
R/W
R/W
Write Only
1000
0100
R/W
Read only
(*) represents revised specification.The test register is now imple-
mented in both chips
REGISTER BIT DEFINITIONS
All bits in the control registers are asserted (true)
when positive. The appropriate status bit answers
to the same address and bit location as the wri-
table bit which causes the action.
This means that when a read is performed, the
actual value read back is not just an echo from
the write register, but represents the status of the
function requested. In most cases this is a direct,
unlatched output from internal circuitry.
Most status bits are reset after being read once.
The control registers have control bits as follows:
Test conditions for serial port timing spec:
Parameter
T
r
, T
f
V
dh
V
dl
V
ch
From/To
SCLK rise, fall
Min.
Max.
5
Units
ns
V
V
V
2.4
0.8
2.4
Note: The serial port must meet these specifications up to the thermal shutdown temperature.
Figure 7. Serial Port Read Timing Waveforms
Figure 8. Serial Port Write Timing Waveforms
L6256
14/28
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| L6258 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:PWM controlled high current DMOS universal motor driver |
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