參數(shù)資料
型號： KU386
廠商： Intel Corp.
英文描述： SX MICROPROCESSOR
中文描述： SX微處理器
文件頁數(shù)： 86/102頁
文件大?。?/td> 1268K
代理商： KU386
Intel386
TM
SX MICROPROCESSOR
Table 9-1. Instruction Set Clock Count Summary
(Continued)
CLOCK COUNT
NOTES
Real
Address
Mode or
Virtual
8086
Mode
Real
INSTRUCTION
FORMAT
Protected Address
Virtual
Address
Mode
Protected
Virtual
Address
Mode
Mode or
Virtual
8086
Mode
REPEATED STRING MANIPULATION
(Continued)
REPNE CMPS
e
Compare String
(Find Match)
1 1 1 1 0 0 1 0
1 0 1 0 0 1 1 w
8086 Mode
Clk Count
Virtual
5
a
9n
**
5
a
9n
**
b
h
REP INS
e
Input String
1 1 1 1 0 0 1 0
0 1 1 0 1 1 0 w
2
13
a
6n
*
7
a
6n
*
/
27
a
6n
*
b
s/t, h, m
REP LODS
e
Load String
1 1 1 1 0 0 1 0
1 0 1 0 1 1 0 w
5
a
6n
*
5
a
6n
*
b
h
REP MOVS
e
Move String
1 1 1 1 0 0 1 0
1 0 1 0 0 1 0 w
7
a
4n
*
7
a
4n
**
b
h
REP OUTS
e
Output String
1 1 1 1 0 0 1 0
0 1 1 0 1 1 1 w
2
12
a
5n
*
6
a
5n
*
/
26
a
5n
*
b
s/t, h, m
REPE SCAS
e
Scan String
(Find Non-AL/AX/EAX)
1 1 1 1 0 0 1 1
1 0 1 0 1 1 1 w
5
a
8n
*
5
a
8n
*
b
h
REPNE SCAS
e
Scan String
(Find AL/AX/EAX)
1 1 1 1 0 0 1 0
1 0 1 0 1 1 1 w
5
a
8n
*
5
a
8n
*
b
h
REP STOS
e
Store String
1 1 1 1 0 0 1 0
1 0 1 0 1 0 1 w
5
a
5n
*
5
a
5n
*
b
h
BIT MANIPULATION
BSF
e
Scan Bit Forward
0 0 0 0 1 1 1 1
1 0 1 1 1 1 0 0 mod reg
r/m
10
a
3n
*
10
a
3n
**
b
h
BSR
e
Scan Bit Reverse
0 0 0 0 1 1 1 1
1 0 1 1 1 1 0 1 mod reg
r/m
10
a
3n
*
10
a
3n
**
b
h
BT
e
Test Bit
Register/Memory, Immediate
0 0 0 0 1 1 1 1
1 0 1 1 1 0 1 0 mod 1 0 0
r/m immed 8-bit data
3/6
*
3/6
*
b
h
Register/Memory, Register
0 0 0 0 1 1 1 1
1 0 1 0 0 0 1 1 mod reg
r/m
3/12
*
3/12
*
b
h
BTC
e
Test Bit and Complement
Register/Memory, Immediate
0 0 0 0 1 1 1 1
1 0 1 1 1 0 1 0 mod 1 1 1
r/m immed 8-bit data
6/8
*
6/8
*
b
h
Register/Memory, Register
0 0 0 0 1 1 1 1
1 0 1 1 1 0 1 1 mod reg
r/m
6/13
*
6/13
*
b
h
BTR
e
Test Bit and Reset
Register/Memory, Immediate
0 0 0 0 1 1 1 1
1 0 1 1 1 0 1 0 mod 1 1 0
r/m immed 8-bit data
6/8
*
6/8
*
b
h
Register/Memory, Register
0 0 0 0 1 1 1 1
1 0 1 1 0 0 1 1 mod reg
r/m
6/13
*
6/13
*
b
h
BTS
e
Test Bit and Set
Register/Memory, Immediate
0 0 0 0 1 1 1 1
1 0 1 1 1 0 1 0 mod 1 0 1
r/m immed 8-bit data
6/8
*
6/8
*
b
h
Register/Memory, Register
0 0 0 0 1 1 1 1
1 0 1 0 1 0 1 1 mod reg
r/m
6/13
*
6/13
*
b
h
CONTROL TRANSFER
CALL
e
Call
Direct Within Segment
1 1 1 0 1 0 0 0
full displacement
7
a
m
*
9
a
m
*
b
r
Register/Memory
Indirect Within Segment
1 1 1 1 1 1 1 1 mod 0 1 0
r/m
7
a
m
*
/10
a
m
*
9
a
m/
12
a
m
*
b
h, r
Direct Intersegment
1 0 0 1 1 0 1 0 unsigned full offset, selector
17
a
m
*
42
a
m
*
b
j,k,r
NOTE:
2
Clock count shown applies if I/O permission allows I/O to the port in virtual 8086 mode. If I/O bit map denies permission
exception 13 fault occurs; refer to clock counts for INT 3 instruction.
86
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