參數(shù)資料
型號(hào)： KU386
廠商： Intel Corp.
英文描述： SX MICROPROCESSOR
中文描述： SX微處理器
文件頁數(shù)： 43/102頁
文件大?。?/td> 1268K
代理商： KU386
Intel386
TM
SX MICROPROCESSOR
questing bus master may control them. These pins
remain OFF throughout the time that HLDA remains
active (see Table 5.3)). Pull-up resistors may be de-
sired on several signals to avoid spurious activity
when no bus master is driving them. See
Resistor
Recommendations
for additional information.
When the HOLD signal is made inactive, the
Intel386 SX Microprocessor will deactivate HLDA
and drive the bus. One rising edge on the NMI input
is remembered for processing after the HOLD input
is negated.
Table 5.3. Output pin State During HOLD
Pin Value Pin Names
1
Float
HLDA
LOCK
Y
, M/IO
Y
, D/C
Y
, W/R
Y
,
ADS
Y
, A
23
–A
1
, BHE
Y
, BLE
Y
, D
15
–D
0
In addition to the normal usage of Hold Acknowl-
edge with DMA controllers or master peripherals,
the near-complete isolation has particular attractive-
ness during system test when test equipment drives
the system, and in hardware fault-tolerant applica-
tions.
HOLD Latencies
The maximum possible HOLD latency depends on
the software being executed. The actual HOLD la-
tency at any time depends on the current bus activi-
ty, the state of the LOCK
Y
signal (internal to the
CPU) activated by the LOCK
Y
prefix, and interrupts.
The Intel386 SX Microprocessor will not honor a
HOLD request until the current bus operation is
complete.
The Intel386 SX Microprocessor breaks 32-bit data
or I/O accesses into 2 internally locked 16-bit bus
cycles; the LOCK
Y
signal is not asserted. The
Intel386 SX Microprocessor breaks unaligned 16-bit
or 32-bit data or I/O accesses into 2 or 3 internally
locked 16-bit bus cycles. Again, the LOCK
Y
signal is
not asserted but a HOLD request will not be recog-
nized until the end of the entire transfer.
Wait states affect HOLD latency. The Intel386 SX
Microprocessor will not honor a HOLD request until
the end of the current bus operation, no matter how
many wait states are required. Systems with DMA
where data transfer is critical must insure that
READY
Y
returns sufficiently soon.
COPROCESSOR INTERFACE SIGNALS
(PEREQ, BUSY
Y
, ERROR
Y
)
In the following sections are descriptions of signals
dedicated to the numeric coprocessor interface. In
addition to the data bus, address bus, and bus cycle
definition signals, these following signals control
communication between the Intel386 SX Microproc-
essor and its Intel387
TM
SX processor extension.
Coprocessor Request (PEREQ)
When asserted (HIGH), this input signal indicates a
coprocessor request for a data operand to be trans-
ferred to/from memory by the Intel386 SX Micro-
processor. In response, the Intel386 SX Microproc-
essor transfers information between the coproces-
sor and memory. Because the Intel386 SX Micro-
processor has internally stored the coprocessor op-
code being executed, it performs the requested data
transfer with the correct direction and memory ad-
dress.
PEREQ is a level-sensitive active HIGH asynchro-
nous signal. Setup and hold times, t
29
and t
30
, rela-
tive to the CLK2 signal must be met to guarantee
recognition at a particular clock edge. This signal is
provided with a weak internal pull-down resistor of
around 20 K-ohms to ground so that it will not float
active when left unconnected.
Coprocessor Busy (BUSY
Y
)
When asserted (LOW), this input indicates the co-
processor is still executing an instruction, and is not
yet able to accept another. When the Intel386 SX
Microprocessor encounters any coprocessor in-
struction which operates on the numerics stack (e.g.
load, pop, or arithmetic operation), or the WAIT in-
struction, this input is first automatically sampled un-
til it is seen to be inactive. This sampling of the
BUSY
Y
input prevents overrunning the execution of
a previous coprocessor instruction.
The
FNSTCW and FNCLEX coprocessor instructions are
allowed to execute even if BUSY
Y
is active, since
these instructions are used for coprocessor initializa-
tion and exception-clearing.
FNINIT,
FNSTENV,
FNSAVE,
FNSTSW,
BUSY
Y
is an active LOW, level-sensitive asynchro-
nous signal. Setup and hold times, t
29
and t
30
, rela-
43
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