參數(shù)資料
型號： KU386
廠商： Intel Corp.
英文描述： SX MICROPROCESSOR
中文描述： SX微處理器
文件頁數(shù)： 54/102頁
文件大?。?/td> 1268K
代理商： KU386
Intel386
TM
SX MICROPROCESSOR
Bus States:
T1Dfirst clock of a non-pipelined bus cycle (Intel386
TM
SX CPU
drives new address and asserts ADS
Y
).
T2Dsubsequent clocks of a bus cycle when NA
Y
has not been
sampled asserted in the current bus cycle.
T2IDsubsequent clocks of a bus cycle when NA
Y
has been
sampled asserted in the current bus cycle but there is not yet
an internal bus request pending (Intel386 SX CPU will not drive
new address or assert ADS
Y
).
T2PDsubsequent clocks of a bus cycle when NA
Y
has been
sampled asserted in the current bus cycle and there is an inter-
nal bus request pending (Intel386 SX CPU drives new address
and asserts ADS
Y
).
T1PDfirst clock of a pipelined bus cycle.
TiDidle state.
ThDhold acknowledge state (Intel386 SX CPU asserts HLDA).
Asserting NA
Y
for pipelined address gives access to three
more bus states: T2I, T2P and T1P.
Using pipelined address, the fastest bus cycle consists of T1P
and T2P.
240187–27
Figure 5.12. Complete Bus States (including pipelined address)
54
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