
Intel386
TM
SX MICROPROCESSOR
Table 9-1. Instruction Set Clock Count Summary
CLOCK COUNT
NOTES
Real
Address
Mode or
Virtual
8086
Mode
Real
Address
Mode or
Virtual
8086
Mode
INSTRUCTION
FORMAT
Protected
Virtual
Address
Mode
Protected
Virtual
Address
Mode
GENERAL DATA TRANSFER
MOV
e
Move:
Register to Register/Memory
1 0 0 0 1 0 0 w
mod reg
r/m
2/2
2/2
*
b
h
Register/Memory to Register
1 0 0 0 1 0 1 w
mod reg
r/m
2/4
2/4
*
b
h
Immediate to Register/Memory
1 1 0 0 0 1 1 w
mod 0 0 0
r/m
immediate data
2/2
2/2
*
b
h
Immediate to Register (short form)
1 0 1 1 w
reg
immediate data
2
2
Memory to Accumulator (short form)
1 0 1 0 0 0 0 w
full displacement
4
*
4
*
b
h
Accumulator to Memory (short form)
1 0 1 0 0 0 1 w
full displacement
2
*
2
*
b
h
Register Memory to Segment Register
1 0 0 0 1 1 1 0
mod sreg3
r/m
2/5
22/23
b
h, i, j
Segment Register to Register/Memory
1 0 0 0 1 1 0 0
mod sreg3
r/m
2/2
2/2
b
h
MOVSX
e
Move With Sign Extension
Register From Register/Memory
0 0 0 0 1 1 1 1
1 0 1 1 1 1 1 w
mod reg
r/m
3/6
*
3/6
*
b
h
MOVZX
e
Move With Zero Extension
Register From Register/Memory
0 0 0 0 1 1 1 1
1 0 1 1 0 1 1 w
mod reg
r/m
3/6
*
3/6
*
b
h
PUSH
e
Push:
Register/Memory
1 1 1 1 1 1 1 1
mod 1 1 0
r/m
5/7
*
7/9
*
b
h
Register (short form)
0 1 0 1 0
reg
2
4
b
h
(short form)
Segment Register (ES, CS, SS, DS,
Segment Register (ES, CS, SS or DS)
0 0 0 sreg2 1 1 0
2
4
b
h
FS or GS)
0 0 0 0 1 1 1 1
1 0 sreg3 0 0 0
2
4
b
h
Immediate
0 1 1 0 1 0 s 0
immediate data
2
4
b
h
PUSHA
e
Push All
0 1 1 0 0 0 0 0
18
34
b
h
POP
e
Pop
Register/Memory
1 0 0 0 1 1 1 1
mod 0 0 0
r/m
5/7
7/9
b
h
Register (short form)
0 1 0 1 1
reg
6
6
b
h
(short form)
Segment Register (ES, CS, SS or DS),
Segment Register (ES, CS, SS or DS)
0 0 0 sreg 2 1 1 1
7
25
b
h, i, j
FS or GS
0 0 0 0 1 1 1 1
1 0 sreg 3 0 0 1
7
25
b
h, i, j
POPA
e
Pop All
0 1 1 0 0 0 0 1
24
40
b
h
XCHG
e
Exchange
Register/Memory With Register
1 0 0 0 0 1 1 w
mod reg
r/m
3/5
**
3/5
**
b, f
f, h
Register With Accumulator (short form)
1 0 0 1 0
reg
8086 Mode
Clk Count
Virtual
3
3
IN
e
Input from:
Fixed Port
1 1 1 0 0 1 0 w
port number
2
26
12
*
6
*
/26
*
s/t,m
Variable Port
1 1 1 0 1 1 0 w
2
27
13
*
7
*
/27
*
s/t,m
OUT
e
Output to:
Fixed Port
1 1 1 0 0 1 1 w
port number
2
24
10
*
4
*
/24
*
s/t,m
Variable Port
1 1 1 0 1 1 1 w
2
25
11
*
5
*
/25
*
s/t,m
LEA
e
Load EA to Register
1 0 0 0 1 1 0 1
mod reg
r/m
2
2
81