參數(shù)資料
型號(hào)： KU386
廠商： Intel Corp.
英文描述： SX MICROPROCESSOR
中文描述： SX微處理器
文件頁數(shù)： 28/102頁
文件大?。?/td> 1268K
代理商： KU386
Intel386
TM
SX MICROPROCESSOR
31
16
0
SEGMENT BASE 15 . . . 0
SEGMENT LIMIT 15 . . . 0
0
BASE 31 . . . 24
G
0
0
0
LIMIT
19 . . . 16
P
DPL
0
TYPE
BASE
23 . . . 16
a
4
Type
Defines
0
1
2
3
4
5
Invalid
Available 80286 TSS
LDT
Busy 80286 TSS
80286 Call Gate
Task Gate (for 80286 or Intel386
TM
SX
Microprocessor Task)
80286 Interrupt Gate
80286 Trap Gate
6
7
Type
Defines
8
9
A
B
C
D
E
F
Invalid
Available Intel386
TM
SX Microprocessor TSS
Undefined (Intel Reserved)
Busy Intel386
TM
SX Microprocessor TSS
Intel386
TM
SX Microprocessor Call Gate
Undefined (Intel Reserved)
Intel386
TM
SX Microprocessor Interrupt Gate
Intel386
TM
SX Microprocessor Trap Gate
Figure 4.6. System Descriptors
Code and data segments have several descriptor
fields in common. The accessed bit, A, is set when-
ever the processor accesses a descriptor. The gran-
ularity bit, G, specifies if a segment length is byte-
granular or page-granular.
System Descriptor Formats (S
e
0)
System segments describe information about oper-
ating system tables, tasks, and gates. Figure 4.6
shows the general format of system segment de-
scriptors, and the various types of system segments.
Intel386 SX system descriptors (which are the same
as Intel386 DX CPU system descriptors) contain a
32-bit base linear address and a 20-bit segment lim-
it. 80286 system descriptors have a 24-bit base ad-
dress and a 16-bit segment limit. 80286 system de-
scriptors are identified by the upper 16 bits being all
zero.
Differences Between Intel386
TM
SX
Microprocessor and 80286 Descriptors
In order to provide operating system compatibility
with the 80286 the Intel386 SX CPU supports all of
the 80286 segment descriptors. The 80286 system
segment descriptors contain a 24-bit base address
and 16-bit limit, while the Intel386 SX CPU system
segment descriptors have a 32-bit base address, a
20-bit limit field, and a granularity bit. The word count
field specifies the number of 16-bit quantities to copy
for 80286 call gates and 32-bit quantities for
Intel386 SX CPU call gates.
Selector Fields
A selector in Protected Mode has three fields: Local
or Global Descriptor Table indicator (TI), Descriptor
Entry Index (Index), and Requestor (the selector’s)
Privilege Level (RPL) as shown in Figure 4.7. The TI
bit selects either the Global Descriptor Table or the
Local Descriptor Table. The Index selects one of 8k
descriptors in the appropriate descriptor table. The
RPL bits allow high speed testing of the selector’s
privilege attributes.
Segment Descriptor Cache
In addition to the selector value, every segment reg-
ister has a segment descriptor cache register asso-
ciated with it. Whenever a segment register’s con-
tents are changed, the 8-byte descriptor associated
with that selector is automatically loaded (cached)
on the chip. Once loaded, all references to that seg-
ment use the cached descriptor information instead
of reaccessing the descriptor. The contents of the
descriptor cache are not visible to the programmer.
Since descriptor caches only change when a seg-
ment register is changed, programs which modify
the descriptor tables must reload the appropriate
segment registers after changing a descriptor’s val-
ue.
28
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