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參數(shù)資料
| 型號(hào)： | KU386 |
| 廠商： | Intel Corp. |
| 英文描述： | SX MICROPROCESSOR |
| 中文描述： | SX微處理器 |
| 文件頁數(shù)： | 45/102頁 |
| 文件大?。?/td> | 1268K |
| 代理商： | KU386 |
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Intel386
TM
SX MICROPROCESSOR
D If the instruction loads the Stack Segment reg-
ister, an interrupt is not processed until after
the following instruction, which should be an
ESP. This allows the entire stack pointer to be
loaded without interruption.
D If an instruction sets the interrupt flag (enabling
interrupts), an interrupt is not processed until
after the next instruction.
The longest latency occurs when the interrupt re-
quest arrives while the Intel386 SX Microproces-
sor is executing a long instruction such as multipli-
cation, division, or a task-switch in the protected
mode.
4. Saving the Flags register and CS:EIP registers.
5. If interrupt service routine requires a task switch,
time must be allowed for the task switch.
6. If the interrupt service routine saves registers that
are not automatically saved by the Intel386 SX
Microprocessor.
RESET
This input signal suspends any operation in progress
and places the Intel386 SX Microprocessor in a
known reset state. The Intel386 SX Microprocessor
is reset by asserting RESET for 15 or more CLK2
periods (80 or more CLK2 periods before requesting
self-test). When RESET is active, all other input pins,
except FLT
Y
, are ignored, and all other bus pins are
driven to an idle bus state as shown in Table 5.5. If
RESET and HOLD are both active at a point in time,
RESET takes priority even if the Intel386 SX Micro-
processor was in a Hold Acknowledge state prior to
RESET active.
RESET is an active HIGH, level-sensitive synchro-
nous signal. Setup and hold times, t
25
and t
26
, must
be met in order to assure proper operation of the
Intel386 SX Microprocessor.
Table 5.5. Pin State (Bus Idle) During Reset
Pin Name
Signal Level During Reset
ADS
Y
D
15
–D
0
BHE
Y
, BLE
Y
A
23
–A
1
W/R
Y
D/C
Y
M/IO
Y
LOCK
Y
HLDA
1
Float
0
1
0
1
0
1
0
5.2 Bus Transfer Mechanism
All data transfers occur as a result of one or more
bus cycles. Logical data operands of byte and word
lengths may be transferred without restrictions on
physical address alignment. Any byte boundary may
be used, although two physical bus cycles are per-
formed as required for unaligned operand transfers.
The Intel386 SX Microprocessor address signals are
designed to simplify external system hardware.
Higher-order address bits are provided by A
23
–A
1
.
BHE
Y
and BLE
Y
provide linear selects for the two
bytes of the 16-bit data bus.
Byte Enable outputs BHE
Y
and BLE
Y
are asserted
when their associated data bus bytes are involved
with the present bus cycle, as listed in Table 5.6.
Table 5.6. Byte Enables and Associated Data
and Operand Bytes
Byte Enable
Signal
Associated Data Bus Signals
BLE
Y
BHE
Y
D
7
–D
0
D
15
–D
8
(byte 1 D most significant)
(byte 0 D least significant)
Each bus cycle is composed of at least two bus
states. Each bus state requires one processor clock
period. Additional bus states added to a single bus
cycle are called wait states. See section
5.4 Bus
Functional Description
.
5.3 Memory and I/O Spaces
Bus cycles may access physical memory space or
I/O space. Peripheral devices in the system may ei-
ther be memory-mapped, or I/O-mapped, or both.
As shown in Figure 5.3, physical memory addresses
range from 000000H to 0FFFFFFH (16 megabytes)
and I/O addresses from 000000H to 00FFFFH
(64 kilobytes). Note the I/O addresses used by the
automatic I/O cycles for coprocessor communica-
tion are 8000F8H to 8000FFH, beyond the address
range of programmed I/O, to allow easy generation
of a coprocessor chip select signal using the A
23
and M/IO
Y
signals.
5.4 Bus Functional Description
The Intel386 SX Microprocessor has separate, par-
allel buses for data and address. The data bus is 16-
bits in width, and bidirectional. The address bus pro-
vides a 24-bit value using 23 signals for the 23 up-
per-order address bits and 2 Byte Enable signals to
directly indicate the active bytes. These buses are
interpreted and controlled by several definition sig-
nals.
The definition of each bus cycle is given by three
signals: M/IO
Y
, W/R
Y
and D/C
Y
. At the same
time, a valid address is present on the byte enable
signals, BHE
Y
and BLE
Y
, and the other address
signals A
23
–A
1
. A status signal, ADS
Y
, indicates
45
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