參數(shù)資料
型號: KSZ8873FLLI
廠商: Micrel Inc
文件頁數(shù): 96/115頁
文件大小: 0K
描述: IC ETHERNET SWITCH 3PORT 64LQFP
產(chǎn)品培訓(xùn)模塊: KSZ8873 Ethernet Switches
標準包裝: 160
控制器類型: 以太網(wǎng)開關(guān)控制器
接口: MII
電源電壓: 1.8V,2.5V,3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
其它名稱: 576-3632
KSZ8873FLLI-ND
Micrel, Inc.
KSZ8873MLL/FLL/RLL
September 20, 2013
81
Revision 1.6
Register 130 (0x82): Indirect Data Register 1
Bit
Name
R/W
Description
Default
7-0
Indirect Data
[15:8]
R/W
Bits [15:8] of indirect data
0000_0000
Register 131 (0x83): Indirect Data Register 0
Bit
Name
R/W
Description
Default
7-0
Indirect Data
[7:0]
R/W
Bits [7:0] of indirect data
0000_0000
Register 147~142(0x93~0x8E): Station MAC Address 1 MACA1
Register 153~148 (0x99~0x94): Station MAC Address 2 MACA2
Bit
Name
R/W
Description
Default
47-0
Station
address
R/W
48-bit Station address MACA1 and MACA2.
Note: This address is used for self MAC address filtering, see the
port register control 5 bits [6,5] for detail.
48’h0
Note: the MSB bit[47-40]
of the MAC is the register
147 and 153.
The LSB bit[7-0] of MAC
is the register 142 and
148.
Register 154[6:0] (0x9A): Port 1 Q0 Egress Data Rate Limit
Register 158[6:0] (0x9E): Port 2 Q0 Egress Data Rate Limit
Register 162[6:0] (0xA2): Port 3 Q0 Egress Data Rate Limit
Bit
Name
R/W
Description
Default
7
Egress Rate
Limit Flow
Control Enable
R/W
=1, Enable egress rate limit flow control.
=0, Disable
0
6-0
Q0 Egress
Data Rate limit
R/W
Egress data rate limit for priority 0 frames
Egress traffic from this priority queue is shaped according to the Data Rate
Limit Table.
0
Register 155[6:0] (0x9B): Port 1 Q1 Egress Data Rate Limit
Register 159[6:0] (0x9F): Port 2 Q1 Egress Data Rate Limit
Register 163[6:0] (0xA3): Port 3 Q1 Egress Data Rate Limit
Bit
Name
R/W
Description
Default
7
Reserved
R/W
Reserved
Do not change the default values.
0
6-0
Q1 Egress
data Rate limit
R/W
Egress data rate limit for priority 1 frames
Egress traffic from this priority queue is shaped according to the Data Rate
Limit Table.
0
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