參數(shù)資料
型號(hào): KSZ8873FLLI
廠商: Micrel Inc
文件頁(yè)數(shù): 75/115頁(yè)
文件大?。?/td> 0K
描述: IC ETHERNET SWITCH 3PORT 64LQFP
產(chǎn)品培訓(xùn)模塊: KSZ8873 Ethernet Switches
標(biāo)準(zhǔn)包裝: 160
控制器類型: 以太網(wǎng)開(kāi)關(guān)控制器
接口: MII
電源電壓: 1.8V,2.5V,3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
其它名稱: 576-3632
KSZ8873FLLI-ND
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Micrel, Inc.
KSZ8873MLL/FLL/RLL
September 20, 2013
62
Revision 1.6
Register 17 (0x11): Port 1 Control 1
Register 33 (0x21): Port 2 Control 1
Register 49 (0x31): Port 3 Control 1
Bit
Name
R/W
Description
Default
7
Sniffer Port
R/W
=1, Port is designated as sniffer port and will transmit packets that are
monitored.
=0, Port is a normal port
0
6
Receive Sniff
R/W
=1, All packets received on the port will be marked as “monitored packets” and
forwarded to the designated “sniffer port”
=0, No receive monitoring
0
5
Transmit Sniff
R/W
=1, All packets transmitted on the port will be marked as “monitored packets”
and forwarded to the designated “sniffer port”
=0, No transmit monitoring
0
4
Double Tag
R/W
=1, All packets will be tagged with port default tag of ingress port regardless of
the original packets are tagged or not
=0, Do not double tagged on all packets
0
3
User Priority
Ceiling
R/W
=1, If the packet’s “user priority field” is greater than the “user priority field” in
the port default tag register, replace the packet’s “user priority field” with the
“user priority field” in the port default tag register.
=0, Do not compare and replace the packet’s ‘user priority field”
0
2-0
Port VLAN
membership
R/W
Define the port’s egress port VLAN membership. The port can only
communicate within the membership. Bit 2 stands for port 3, bit 1 stands for
port 2, bit 0 stands for port 1.
An ‘1’ includes a port in the membership.
An ‘0’ excludes a port from membership.
111
Register 18 (0x12): Port 1 Control 2
Register 34 (0x22): Port 2 Control 2
Register 50 (0x32): Port 3 Control 2
Bit
Name
R/W
Description
Default
7
Enable 2 Queue
Split of Tx Queue
R/W
=1, Enable
It cannot be enabled at the same time with split 4 queue at register 16, 32, and
48 bit 0.
=0, Disable
0
6
Ingress VLAN
Filtering
R/W
=1,The switch will discard packets whose VID port membership in VLAN table
bits [18:16] does not include the ingress port.
=0, No ingress VLAN filtering.
0
5
Discard non PVID
Packets
R/W
=1, The switch will discard packets whose VID does not match ingress port
default VID.
=0, No packets will be discarded
0
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