參數(shù)資料
型號(hào): KSZ8841-16MQL-EVAL
廠商: Micrel Inc
文件頁(yè)數(shù): 75/105頁(yè)
文件大?。?/td> 0K
描述: BOARD EVALUATION KSZ8841-16MQL
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,以太網(wǎng)控制器(PHY 和 MAC)
嵌入式:
已用 IC / 零件: KSZ8841-16MQL
主要屬性: 1 個(gè)端口,100BASE-TX/10BASE-T
次要屬性: 8/16 位接口,LinkMD 線纜診斷
已供物品: 板,CD,文檔,電源
相關(guān)產(chǎn)品: KSZ8841-16MQL A6-ND - IC MAC CTRLR 8/16BIT 128-PQFP
576-2115-ND - IC MAC CTRLR 32BIT 128-PQFP
576-2112-ND - IC MAC CTRLR 8/16BIT 128-PQFP
其它名稱: 576-1631
Micrel, Inc.
KSZ8841-16/32 MQL/MVL/MBL
October 2007
71
M9999-102207-1.6
Bank 18 Early Transmit Register (0x08): ETXR
This register specifies the threshold for the early transmit.
Bit
Default Value
R/W
Description
15-8
-
RO
Reserved.
7
0x0
RW
TXEE Early Transmit Enable
When this bit is set, the Early Transmit function is enabled.
When this bit is cleared, normal operation is assumed.
6-5
-
RO
Reserved.
4-0
0x00
RW
ETXTH Early Transmit Threshold
The threshold for Early Transmit. Specified in unit of 64-byte. Whenever the number of bytes
written in memory for the presently transmitting packet exceeds the threshold, Early Transmit
will be started on the network interface.
When early transmit is enabled, setting this field to 0 is invalid, and the hardware behavior is
unknown.
Bank 18 Early Receive Register (0x0A): ERXR
This register specify the threshold for early receive and interrupt condition.
Bit
Default Value
R/W
Description
15-8
-
RO
Reserved.
7
0x0
RW
RXEE Early Receive Enable
When this bit is set, the Early Receive function is enabled.
When this bit is cleared, normal operation is assumed.
6-5
-
RO
Reserved.
4-0
0x1F
RW
ERXTH Early Receive Threshold
The threshold for Early Receive and Interrupt. Specified in unit of 64-byte. Whenever the
number of bytes written in memory for the presently received packet exceeds the threshold,
early receive status will be set, and Early Receive interrupt will be asserted if its interrupt is
enabled.
When early receive is enabled, setting this field to 0 is invalid, and the hardware behavior is
unknown.
Bank 19 Multicast Table Register 0 (0x00): MTR0
The 64-bit multicast table is used for group address filtering. This value is defined as the six most significant bits from
CRC circuit calculation result that is based on 48-bit of DA input. The two most significant bits select one of the four
registers to be used, while the others determine which bit within the register.
Multicast table register 0.
Bit
Default Value
R/W
Description
15-0
0x0
RW
MTR0 Multicast Table 0
When the appropriate bit is set, if the packet received with DA matches the CRC, the hashing
function is received without being filtered.
When the appropriate bit is cleared, the packet will drop.
Note: When the receive all (RXRA) or receive multicast (RXRM) bit is set in the RXCR, all
multicast addresses are received regardless of the multicast table value.
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