參數(shù)資料
型號: KSZ8841-16MQL-EVAL
廠商: Micrel Inc
文件頁數(shù): 21/105頁
文件大?。?/td> 0K
描述: BOARD EVALUATION KSZ8841-16MQL
標準包裝: 1
主要目的: 接口,以太網(wǎng)控制器(PHY 和 MAC)
嵌入式:
已用 IC / 零件: KSZ8841-16MQL
主要屬性: 1 個端口,100BASE-TX/10BASE-T
次要屬性: 8/16 位接口,LinkMD 線纜診斷
已供物品: 板,CD,文檔,電源
相關(guān)產(chǎn)品: KSZ8841-16MQL A6-ND - IC MAC CTRLR 8/16BIT 128-PQFP
576-2115-ND - IC MAC CTRLR 32BIT 128-PQFP
576-2112-ND - IC MAC CTRLR 8/16BIT 128-PQFP
其它名稱: 576-1631
Micrel, Inc.
KSZ8841-16/32 MQL/MVL/MBL
October 2007
22
M9999-102207-1.6
Pin Description for KSZ8841-32 Chip (32-Bit)
Pin Number
Pin Name
Type
Pin Function
1
TEST_EN
I
Test Enable
For normal operation, pull-down this pin-to-ground.
2
SCAN_EN
I
Scan Test Scan Mux Enable
For normal operation, pull-down this pin-to-ground.
3
P1LED2
Opu
4
P1LED1
Opu
5
P1LED0
Opu
Port 1 LED indicators
1 defined as follows:
Chip Global Control Register: CGCR
bit [15,9]
[0,0] Default
[0,1]
P1LED3
2
P1LED2
Link/Act
100Link/Act
P1LED1
Full duplex/Col
10Link/Act
P1LED0
Speed
Full duplex
Reg. CGCR bit [15,9]
[1,0]
[1,1]
P1LED3
2
Act
P1LED2
Link
P1LED1
Full duplex/Col
P1LED0
Speed
Notes:
1. Link = On; Activity = Blink; Link/Act = On/Blink; Full Dup/Col = On/Blink;
Full Duplex = On (Full duplex); Off (Half duplex)
Speed = On (100BASE-T); Off (10BASE-T)
2. P1LED3 is pin 27.
6
NC
Opu
No Connect.
7
NC
Opu
No Connect.
8
NC
Opu
No Connect.
9
DGND
Gnd
Digital ground
10
VDDIO
P
3.3V digital VDDIO input power supply for IO with well decoupling capacitors.
11
RDYRTNN
Ipd
Ready Return Not:
For VLBus-like mode: Asserted by the host to complete synchronous read cycles. If the
host doesn’t connect to this pin, assert this pin.
For burst mode (32-bit interface only): Host drives this pin low to signal waiting states.
12
BCLK
Ipd
Bus Interface Clock
Local bus clock for synchronous bus systems. Maximum frequency is 50MHz.
This pin should be tied Low or unconnected if it is in asynchronous mode.
13
DATACSN
Ipu
DATA Chip Select Not (For KSZ8841-32 Mode only)
Chip select signal for QMU data register (QDRH, QDRL), active Low.
When DATACSN is Low, the data path can be accessed regardless of the value of AEN,
A15-A1, and the content of the BANK select register.
14
PMEN
Opu
Power Management Event Not
When asserted (Low), this signal indicates that a power management event has occurred
in the system when a wake-up signal is detected by KSZ8841M.
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