參數(shù)資料
型號: KSZ8841-16MQL-EVAL
廠商: Micrel Inc
文件頁數(shù): 59/105頁
文件大小: 0K
描述: BOARD EVALUATION KSZ8841-16MQL
標準包裝: 1
主要目的: 接口,以太網(wǎng)控制器(PHY 和 MAC)
嵌入式:
已用 IC / 零件: KSZ8841-16MQL
主要屬性: 1 個端口,100BASE-TX/10BASE-T
次要屬性: 8/16 位接口,LinkMD 線纜診斷
已供物品: 板,CD,文檔,電源
相關(guān)產(chǎn)品: KSZ8841-16MQL A6-ND - IC MAC CTRLR 8/16BIT 128-PQFP
576-2115-ND - IC MAC CTRLR 32BIT 128-PQFP
576-2112-ND - IC MAC CTRLR 8/16BIT 128-PQFP
其它名稱: 576-1631
Micrel, Inc.
KSZ8841-16/32 MQL/MVL/MBL
October 2007
57
M9999-102207-1.6
Bit
Default Value
R/W
Description
(PMEN pin 14) in D0 power state.
10
0
RO
D2 Support
If this bit is set, it indicates that the KSZ8841M support D2 power state. The value of
this bit is loaded from the D2_SUP bit of 0x6 in the serial EEPROM (without an
EEPROM, this bit defaults to 0).
9
0
RO
D1 Support
If this bit is set, it indicates that the KSZ8841M support D1 power state. The value of
this bit is loaded from the D1_SUP bit of 0x6 in the serial EEPROM (without an
EEPROM, this bit defaults to 0).
8-1
-
RO
Reserved.
0
-
RO
Bus Configuration (only for KSZ8841-16MQL device)
1: bus width is 16 bits.
0: bus width is 8 bits.
(this bit, ASYN_8bit, is only avaiable when EEPROM is enabled)
Bank 3 Wakeup Frame Control Register (0x0A): WFCR
This register holds control information programmed by the CPU to control the wake up frame function.
Bit
Default Value
R/W
Description
15-8
0x00
RO
Reserved.
7
0
RW
MPRXE
Magic Packet RX Enable
When set, it enables the magic packet pattern detection.
When reset, the magic packet pattern detection is disabled.
6-4
0x0
RO
Reserved.
3
0
RW
WF3E
Wake up Frame 3 Enable
When set, it enables the Wake up frame 3 pattern detection.
When reset, the Wake up frame 3 pattern detection is disabled.
2
0
RW
WF2E
Wake up Frame 2 Enable
When set, it enables the Wake up frame 2 pattern detection.
When reset, the Wake up frame 2 pattern detection is disabled.
1
0
RW
WF1E
Wake up Frame 1 Enable
When set, it enables the Wake up frame 1 pattern detection.
When reset, the Wake up frame 1 pattern detection is disabled.
0
RW
WF0E
Wake up Frame 0 Enable
When set, it enables the Wake up frame 0 pattern detection.
When reset, the Wake up frame 0 pattern detection is disabled.
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