參數(shù)資料
型號(hào)： KSZ8841-16MQL-EVAL
廠商： Micrel Inc
文件頁(yè)數(shù)： 15/105頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION KSZ8841-16MQL
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，以太網(wǎng)控制器（PHY 和 MAC）
嵌入式： 否
已用 IC / 零件： KSZ8841-16MQL
主要屬性： 1 個(gè)端口，100BASE-TX/10BASE-T
次要屬性： 8/16 位接口，LinkMD 線纜診斷
已供物品： 板，CD，文檔，電源
相關(guān)產(chǎn)品： KSZ8841-16MQL A6-ND - IC MAC CTRLR 8/16BIT 128-PQFP
576-2115-ND - IC MAC CTRLR 32BIT 128-PQFP
576-2112-ND - IC MAC CTRLR 8/16BIT 128-PQFP
其它名稱： 576-1631
Micrel, Inc.
KSZ8841-16/32 MQL/MVL/MBL
October 2007
17
M9999-102207-1.6
Ball Description for KSZ8841-16 Chip (8/16-Bit)
Ball Number
Ball Name
Type
Ball Function
E8
TEST_EN
I
Test Enable
For normal operation, pull-down this ball to ground.
D10
SCAN_EN
I
Scan Test Scan Mux Enable
For normal operation, pull-down this ball to ground.
A10
P1LED2
Opu
B10
P1LED1
Opu
C10
P1LED0
Opu
Port 1 LED indicators
1 defined as follows:
Switch Global Control Register 5:
SGCR5 bit [15,9]
[0,0] Default
[0,1]
P1LED3
2
—
P1LED2
Link/Act
100Link/Act
P1LED1
Full duplex/Col
10Link/Act
P1LED0
Speed
Full duplex
Reg. SGCR5 bit [15,9]
[1,0]
[1,1]
P1LED3
2
Act
—
P1LED2
Link
—
P1LED1
Full duplex/Col
—
P1LED0
Speed
—
Notes:
1. Link = On; Activity = Blink; Link/Act = On/Blink; Full Dup/Col = On/Blink;
Full Duplex = On (Full duplex); Off (Half duplex)
Speed = On (100BASE-T); Off (10BASE-T)
2. P1LED3 is ball A4.
D9
RDYRTNN
Ipd
Ready Return Not:
For VLBus-like mode: Asserted by the host to complete synchronous read
cycles. If the host doesn’t connect to this ball, assert this ball.
A8
BCLK
Ipd
Bus Interface Clock
Local bus clock for synchronous bus systems. Maximum frequency is 50MHz.
This ball should be tied Low or unconnected if it is in asynchronous mode.
D8
PMEN
Opu
Power Management Event Not
When asserted (Low), this signal indicates that a power management event has
occurred in the system when a wake-up signal is detected by KSZ8841M.
B8
SRDYN
Opu
Synchronous Ready Not
Ready signal to interface with synchronous bus for both EISA-like and VLBus-
like extend accesses.
For VLBus-like mode, the falling edge of this signal indicates ready. This signal
is synchronous to the bus clock signal BCLK.
C8
INTRN
Opd
Interrupt
Active Low signal to host CPU to indicate an interrupt status bit is set, this ball
need an external 4.7K pull-up resistor.
A7
LDEVN
Opd
Local Device Not
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
KSZ8841-16MVL 功能描述:以太網(wǎng) IC Single Ethernet Port + Generic (8, 16-bit) bus interface(Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
KSZ8841-16MVL TR 功能描述:以太網(wǎng) IC Single Ethernet Port + Generic (8, 16-bit) bus interface(Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
KSZ8841-16MVL-EVAL 功能描述:BOARD EVALUATION KSZ8841-16MVL RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 過(guò)時(shí)/停產(chǎn)零件編號(hào) 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:MCU 適用于相關(guān)產(chǎn)品:Freescale MC68HC908LJ/LK（80-QFP ZIF 插口） 所含物品:面板、纜線、軟件、數(shù)據(jù)表和用戶手冊(cè) 其它名稱:520-1035
KSZ8841-16MVLI 功能描述:以太網(wǎng) IC Single Ethernet Port + Generic (8, 16-bit) bus interface(Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
KSZ8841-16MVLI TR 功能描述:以太網(wǎng) IC Single Ethernet Port + Generic (8, 16-bit) bus interface(Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
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