- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373155 > KM418RD4AD (SAMSUNG SEMICONDUCTOR CO. LTD.) 128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM PDF資料下載
參數(shù)資料
| 型號： | KM418RD4AD |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| 中文描述： | 128/144Mbit RDRAM的256 × 16/18位× 2 * 16屬銀行直接RDRAMTM |
| 文件頁數(shù)： | 6/64頁 |
| 文件大?。?/td> | 4052K |
| 代理商： | KM418RD4AD |
第1頁第2頁第3頁第4頁第5頁當(dāng)前第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
Page 3
KM416RD8AC(D)/KM418RD8AC(D)
Direct RDRAM
Rev. 1.01 Oct. 1999
Table 3: Pin Description
I/O
Type
# of Pins
Description
SIO1,SIO0
I/O
CMOS
a
2
Serial input/output. Pins for reading from and writing to the control
registers using a serial access protocol. Also used for power man-
agement.
CMD
I
CMOS
a
1
Command input. Pins used in conjunction with SIO0 and SIO1 for
reading from and writing to the control registers. Also used for
power management.
SCK
I
CMOS
a
1
Serial clock input. Clock source used for reading from and writing to
the control registers
V
DD
10
Supply voltage for the RDRAM core and interface logic.
V
DDa
1
Supply voltage for the RDRAM analog circuitry.
V
CMOS
2
Supply voltage for CMOS input/output pins.
GND
13
Ground reference for RDRAM core and interface.
GNDa
1
Ground reference for RDRAM analog circuitry.
DQA8..DQA0
I/O
RSL
b
9
Data byte A. Nine pins which carry a byte of read or write data
between the Channel and the RDRAM. DQA8 is not used by
RDRAMs with a x16 organization.
CFM
I
RSL
b
1
Clock from master. Interface clock used for receiving RSL signals
from the Channel. Positive polarity.
CFMN
I
RSL
b
1
Clock from master. Interface clock used for receiving RSL signals
from the Channel. Negative polarity
V
REF
1
Logic threshold reference voltage for RSL signals
CTMN
I
RSL
b
1
Clock to master. Interface clock used for transmitting RSL signals
to the Channel. Negative polarity.
CTM
I
RSL
b
1
Clock to master. Interface clock used for transmitting RSL signals
to the Channel. Positive polarity.
RQ7..RQ5 or
ROW2..ROW0
I
RSL
b
3
Row access control. Three pins containing control and address
information for row accesses.
RQ4..RQ0 or
COL4..COL0
I
RSL
b
5
Column access control. Five pins containing control and address
information for column accesses.
DQB8..
DQB0
I/O
RSL
b
9
Data byte B. Nine pins which carry a byte of read or write data
between the Channel and the RDRAM. DQB8 is not used by
RDRAMs with a x16 organization.
Total pin count per package
62
a. All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero.
b. All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| KM418RD4C | 128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM418RD4D | 128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM416RD16AD | CAP ELECT 47UF 100V TG SMD |
| KM416RD16C | 15VPP 74DB 2 TERM CERAM BUZZER |
| KM416RD16D | 15VPP 86DB 2 TERM CERAM BUZZER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KM418RD4C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM418RD4D | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM418RD8AC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM418RD8AC(D)-RG60 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM418RD8AC(D)-RK70 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。