參數(shù)資料
型號(hào)： KM418RD4AD
廠(chǎng)商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
中文描述： 128/144Mbit RDRAM的256 × 16/18位× 2 * 16屬銀行直接RDRAMTM
文件頁(yè)數(shù)： 38/64頁(yè)
文件大?。?/td> 4052K
代理商： KM418RD4AD
Page 35
KM416RD8AC(D)/KM418RD8AC(D)
Direct RDRAM
Rev. 1.01 Oct. 1999
.
Figure 36: NAPX Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
DQS
NAPX4..0
NAPXA4..0
Control Register: NAPX
Address: 045
16
Read/write register.
Reset value is undefined
Note - t
SCYCLE
is t
CYCLE1
(SCK cycle time).
NAPXA4..0 - Nap Exit Phase A. This field specifies
the number of SCK cycles during the first phase for
exiting NAP mode. It must satisfy:
NAPXAt
SCYCLE
≥
t
NAPXA,MAX
Do not set this field to zero.
NAPX4..0 - Nap Exit Phase A plus B. This field specifies the number of SCK
cycles during the first plus second phases for exiting NAP mode. It must satisfy:
NAPXt
SCYCLE
≥
NAPXAt
SCYCLE
+t
NAPXB,MAX
Do not set this field to zero.
DQS - DQ Select. This field specifies the number of SCK cycles (0 => 0.5
cycles, 1 => 1.5 cycles) between the CMD pin framing sequence and the device
selection on DQ5..0. See Figure 48 - This field must be written with a
″
1
″
for
this RDRAM.
Figure 37: PDNXA Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
PDNXA12..0
Read/write register.
Reset value is undefined
PDNXA4..0 - PDN Exit Phase A. This field specifies
the number of (64SCK cycle) units during the first
phase for exiting PDN mode. It must satisfy:
PDNXA64t
SCYCLE
≥
t
PDNXA,MAX
Do not set this field to zero.
Note - only PDNXA5..0 are implemented.
Note - t
SCYCLE
is t
CYCLE1
(SCK cycle time).
Control Register: PDNXA
Address: 046
16
Figure 38: PDNX Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
PDNX12..0
Read/write register.
Reset value is undefined
PDNX4..0 - PDN Exit Phase A plus B. This field spec-
ifies the number of (256SCK cycle) units during the
first plus second phases for exiting PDN mode. It must
satisfy:
PDNX256t
SCYCLE
≥
PDNXA64t
SCYCLE
+
t
PDNXB,MAX
If this equation can’t be satisfied, then the maximum
PDNX value should be written, and the t
S4
/t
H4
timing
window will be modified (see Figure 49)
Do not set this field to zero.
Note - only PDNX2..0 are implemented.
Note - t
SCYCLE
is t
CYCLE1
(SCK cycle time).
Control Register: PDNX
Address: 047
16
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
KM418RD4C 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
KM418RD4D 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
KM418RD8AC 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
KM418RD8AC(D)-RG60 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
KM418RD8AC(D)-RK70 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
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