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參數(shù)資料
| 型號： | KM418RD4AD |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| 中文描述： | 128/144Mbit RDRAM的256 × 16/18位× 2 * 16屬銀行直接RDRAMTM |
| 文件頁數(shù)： | 49/64頁 |
| 文件大?。?/td> | 4052K |
| 代理商： | KM418RD4AD |
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Page 46
KM416RD8AC(D)/KM418RD8AC(D)
Direct RDRAM
Rev. 1.01 Oct. 1999
Electrical Characteristics
Timing Characteristics
Table 20: Electrical Characteristics
Symbol
Parameter and Conditions
Min
Max
Unit
Θ
JC
Junction-to-Case thermal resistance
-
0.2
°
C/Watt
I
REF
V
REF
current @ V
REF,MAX
-10
10
μ
A
I
OH
RSL output high current @ (0
≤
V
OUT
≤
V
DD
)
-10
10
μ
A
I
ALL
RSL I
OL
current @ V
OL
= 0.9V, V
DD,MIN
, T
J,MAXa
30.0
90.0
mA
I
OL
RSL I
OL
current resolution step
-
2.0
mA
r
OUT
Dynamic output impedance
150
-
I
I,CMOS
CMOS input leakage current @ (0
≤
V
I,CMOS
≤
V
CMOS
)
-10.0
10.0
μ
A
V
OL,CMOS
CMOS output voltage @ I
OL,CMOS
= 1.0mA
-
0.3
V
V
OH,CMOS
CMOS output high voltage @ I
OH,CMOS
= -0.25mA
V
CMOS
-0.3
-
V
a. This measurement is made in manual current control mode; i.e. with all output device legs sinking current.
Table 21: Timing Characteristics
Symbol
Parameter
Min
Max
Unit
Figure(s)
tQ
CTM-to-DQA/DQB output time
@ tCYCLE=3.33ns
@ tCYCLE=2.81ns
@ tCYCLE=2.50ns
-0.350
a,c
-0.300
b,c
-0.260
c
+0.350
a,c
+0.300
b,c
+0.260
c
ns
Figure 55
t
QR
, t
QF
DQA/DQB output rise and fall times
0.2
0.45
ns
Figure 55
t
Q1
SCK(neg)-to-SIO0 delay @ C
LOAD,MAX
= 20pF (SD read data valid).
-
10
ns
Figure 58
t
HR
SCK(pos)-to-SIO0 delay @ C
LOAD,MAX
= 20pF (SD read data hold).
2
-
ns
Figure 58
t
QR1
, t
QF1
SIO
OUT
rise/fall @ C
LOAD,MAX
= 20pF
-
5
ns
Figure 58
t
PROP1
SIO0-to-SIO1 or SIO1-to-SIO0 delay @ C
LOAD,MAX
= 20pF
-
10
ns
Figure 58
t
NAPXA
NAP exit delay - phase A
-
50
ns
Figure 48
t
NAPXB
NAP exit delay - phase B
-
40
ns
Figure 48
t
PDNXA
PDN exit delay - phase A
-
4
μ
s
Figure 48
t
PDNXB
PDN exit delay - phase B
-
9000
t
CYCLE
Figure 48
t
AS
ATTN-to-STBY power state delay
-
1
t
CYCLE
Figure 46
t
SA
STBY-to-ATTN power state delay
-
0
t
CYCLE
Figure 46
t
ASN
ATTN/STBY-to-NAP power state delay
-
8
t
CYCLE
Figure 47
t
ASP
ATTN/STBY-to-PDN power state delay
-
8
t
CYCLE
Figure 47
a. This parameter also applies to a -800 or -711 part when operated with t
CYCLE
=3.33ns.
b. This parameter also applies to a -800 part when operated with t
CYCLE
=2.81ns.
c. t
Q,MIN
and t
Q,MAX
for other t
CYCLE
values can be interpolated between or extrapolated from the timings at the 3 specified t
CYCLE
values.
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|---|---|
| KM418RD4C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM418RD4D | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM418RD8AC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM418RD8AC(D)-RG60 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM418RD8AC(D)-RK70 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
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