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參數(shù)資料
| 型號： | KM29W040AT |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512K x 8 bit NAND Flash Memory |
| 中文描述： | 為512k × 8位NAND快閃記憶體 |
| 文件頁數(shù)： | 8/22頁 |
| 文件大?。?/td> | 359K |
| 代理商： | KM29W040AT |
KM29W040AT, KM29W040AIT
FLASH MEMORY
8
AC Characteristics for Operation
NOTE
: 1. If CE goes high within 50ns after the third address input, R/B will not return to V
OL
.
2. The time to Ready depends on the value of the pull-up resistor tied R/B pin.
Parameter
Symbol
Min
Max
Unit
Data Transfer from Cell to Register
t
R
-
15
μ
s
ALE to RE Delay
t
AR
250
-
ns
CE low to RE low (ID read)
t
CR
250
-
ns
Ready to RE Low
t
RR
100
-
ns
RE Pulse Width
t
RP
60
-
ns
WE High to Busy
t
WB
-
200
ns
Read Cycle Time
t
RC
120
-
ns
RE Access Time
t
REA
-
50
ns
RE High to Output Hi-Z
t
RHZ
0
30
ns
CE High to Output Hi-Z
t
CHZ
-
50
ns
RE High Hold Time
t
REH
40
-
ns
Output Hi-Z to RE Low
t
IR
0
-
ns
CE High to Ready(in case of interception by CE at read)
(1)
t
CRY
-
100+tr(R/B)
(2)
ns
RE Low to Status Output
t
RSTO
-
60
ns
CE Low to Status Output
t
CSTO
-
70
ns
WE High to RE Low
t
WHR
50
-
ns
RE access time(Read ID)
t
WHRID
100
-
ns
Device Resetting Time
(Read/Program/Erase)
t
RST
-
5/10/500
μ
s
AC Timing Characteristics for Command / Address / Data Input
Parameter
Symbol
Min
Max
Unit
CLE Set-up Time
t
CLS
50
-
ns
CLE Hold Time
t
CLH
50
-
ns
CE Setup Time
t
CS
50
-
ns
CE Hold Time
t
CH
50
-
ns
WE Pulse Width
t
WP
60
-
ns
ALE Setup Time
t
ALS
50
-
ns
ALE Hold Time
t
ALH
50
-
ns
Data Set-up Time
t
DS
40
-
ns
Data Hold Time
t
DH
20
-
ns
Write Cycle Time
t
WC
120
-
ns
WE High Hold Time
t
WH
40
-
ns
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