KM29W040AT, KM29W040AIT
FLASH MEMORY
2
512K x 8 Bit NAND Flash Memory
The KM29W040A is a 512Kx8bit NAND Flash Memory. Its
NAND cell structure provides the most cost-effective solution
for Digital Audio Recording. A Program operation programs a
32-byte frame in typically 500
μ
s and an Erase operation erase
a 4K-byte block in typically 6ms. Data in a frame can be read
out at a burst cycle rate of 120ns/byte. The I/O pins serve as
the ports for address and data input/output as well as for com-
mand inputs. The on-chip write controller automates the pro-
gram and erase operations, including program or erase pulse
repetition where required, and performs internal verification of
cell data.
The KM29W040A is an optimum solution for flash memory
application that do not require the high performance levels or
capacity of larger density flash memories. These application
include data storage in digital Telephone Answering
Devices(TAD) and other consumer applications that require
voice data storage.
GENERAL DESCRIPTION
FEATURES
Voltage Supply: 3.0V~5.5V
Organization
- Memory Cell Array : 512K x 8
- Data Register : 32 x 8 bit
Automatic Program and Erase (Typical)
- Frame Program : 32 Byte in 500
μ
s
- Block Erase : 4K Byte in 6ms
32-Byte Frame Read Operation
- Random Access : 15
μ
s(Max.)
- Serial Frame Access : 120ns(Min.)
Command/Address/Data Multiplexed I/O port
Low Operation Current (Typical)
- 10
μ
A Standby Current
- 10mA Read/ Program/Erase Current
Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
44(40) - Lead TSOP Type II (400mil / 0.8 mm pitch)
PIN CONFIGURATION
VSS
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
I/O0
I/O1
I/O2
I/O3
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
VCC
I/O4
I/O5
I/O6
I/O7
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
GND
R/B
RE
CE
VCC
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
44(40) TSOP (II)
NOTE
: Connect all V
CC
and V
SS
pins of each device to common power supply outputs.
Do not leave V
CC,
V
SS
or GND inputs disconnected.
PIN DESCRIPTION
Pin Name
Pin Function
I/O
0
~ I/O
7
Data Inputs/Outputs
CLE
Command Latch Enable
ALE
Address Latch Enable
CE
Chip Enable
RE
Read Enable
WE
Write Enable
WP
Write Protect
GND
Ground Input
R/B
Ready/Busy output
V
CC
Power
V
SS
Ground
N.C
No Connection