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參數(shù)資料
| 型號： | KM29W040AT |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512K x 8 bit NAND Flash Memory |
| 中文描述： | 為512k × 8位NAND快閃記憶體 |
| 文件頁數(shù)： | 7/22頁 |
| 文件大?。?/td> | 359K |
| 代理商： | KM29W040AT |
KM29W040AT, KM29W040AIT
FLASH MEMORY
7
CAPACITANCE
(
T
A
=25
°
C, Vcc=5.0V, f=1.0MHz)
NOTE
: Capacitance is periodically sampled and not 100% tested.
Item
Symbol
Test Condition
Min
Max
Unit
Input / Output Capacitance
C
I/O
V
IL
=0V
-
10
pF
Input Capacitance
C
IN
V
IN
=0V
-
10
pF
VALID BLOCK
NOTE
:
1. The KM29W040A may include invalid blocks. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try to access these invalid
blocks for program and erase. During its lifetime of 10 years and/or 100K program/erase cycles,the minimum number of valid blocks are guaranteed
though its initial number could be reduced. (Refer to the attached technical notes)
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block
Parameter
Symbol
Min
Typ.
Max
Unit
Valid Block Number
N
VB
125
-
128
Block
Program/Erase Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Program Time
t
PROG
-
0.5
1
ms
Number of Partial Program Cycles in the Same Frame
Nop
-
-
10
cycles
Block Erase Time
t
BERS
-
6
10
ms
MODE SELECTION
NOTE
: 1. X can be V
IL
or V
IH
2. WP should be biased to CMOS high or CMOS low for standby.
CLE
ALE
CE
WE
RE
WP
Mode
H
L
L
H
X
Read Mode
Command Input
L
H
L
H
X
Address Input(3clock)
H
L
L
H
H
Write Mode
Command Input
L
H
L
H
H
Address Input(3clock)
L
L
L
H
H
Data Input
L
L
L
H
X
Sequential Read & Data Output
L
L
L
H
H
X
During Read(Busy)
X
X
X
X
X
H
During Program(Busy)
X
X
X
X
X
H
During Erase(Busy)
X
X
(1)
X
X
X
L
Write Protect
X
X
H
X
X
0V/V
CC
(2)
Stand-by
AC TEST CONDITION
(KM29W040AT:T
A
=0 to 70
°
C, KM29W040AIT:T
A
=-40 to 85
°
C
,
V
CC
=3.0V ~ 5.5V unless otherwise noted)
Parameter
Value
Vcc=3.0V ~ 3.6V
0.4V to 2.6V
Vcc=3.6V ~ 5.5V
0.4V to 2.6V
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
5ns
0.8V and 2.0V
1 TTL GATE and CL = 100pF
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