參數(shù)資料
型號(hào)： K9F1G08Q0A
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： FLASH MEMORY
中文描述： 閃存
文件頁(yè)數(shù)： 35/37頁(yè)
文件大?。?/td> 677K
代理商： K9F1G08Q0A
FLASH MEMORY
35
K9F1G08U0A
K9F1G08Q0A
Figure 14. Read ID Operation
CE
CLE
I/O
X
ALE
RE
WE
90h
00h
Address. 1cycle
Maker code
Device code
t
CEA
t
AR
t
REA
Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Four read cycles sequentially output the manufacturer code(ECh), and the device code and XXh, 4th cycle ID, respectively. The
command register remains in Read ID mode until further commands are issued to it. Figure 14 shows the operation sequence.
Device
Code*
XXh
4th Cyc.*
ECh
Figure 15. RESET Operation
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to table 3 for device status after reset operation.If the device is
already in reset state a new reset command will be accepted by the command register. The R/B pin transitions to low for tRST after
the Reset command is written. Refer to Figure 15 below.
FFh
I/O
X
R/B
t
RST
t
WHR
t
CLR
Device
Device Code*(2nd Cycle)
4th Cycle*
K9F1G08Q0A
A1h
15h
K9F1G08U0A
F1h
15h
Table3. Device Status
After Power-up
After Reset
Operation Mode
00h command is latched
Waiting for next command
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參數(shù)描述
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