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K8S5615ETC
datasheet NOR FLASH MEMORY
Rev. 1.0
[Table 10] Burst Mode Configuration Register Table : K8S54(55)15ET(B)(Z)C : 66/83/108/133Mhz with the Sync MRS option
NOTE :
Initial wait state should be set according to it’s clock frequency. Table 10 recommend the program wait state for each clock frequencies.
Not 100% tested
[Table 11] Burst Mode Configuration Register Table : K8S56(57)15ET(B)(Z)C : 66/83/108/133Mhz with no option
NOTE :
Initial wait state should be set according to it’s clock frequency. Table 11 recommend the program wait state for each clock frequencies.
Not 100% tested
[Table 12] Burst Address Sequences
Address Bit
Function
Settings(Binary)
A19
Read Mode
1 = Synchronous Burst Read Mode
0 = Asynchronous Read Mode (default)
A18
RDY Active
1 = RDY active one clock cycle before data
0 = RDY active with data(default)
A17
Burst Read Mode
000 = Continuous(default)
001 = 8-word linear with wrap
010 = 16-word linear with wrap
011~111 = Reserve
A16
A15
A14
Programmable Wait State
0000 = Data is valid on the 4th active CLK edge after AVD transition to VIH
0001 = Data is valid on the 5th active CLK edge after AVD transition to VIH (40Mhz*)
0010 = Data is valid on the 6th active CLK edge after AVD transition to VIH (50/54Mhz*)
0011 = Data is valid on the 7th active CLK edge after AVD transition to VIH (60/66Mhz*)
0100 = Data is valid on the 8th active CLK edge after AVD transition to VIH (70Mhz*)
0101 = Data is valid on the 9th active CLK edge after AVD transition to VIH (80/83Mhz*)
0110 = Data is valid on the 10th active CLK edge after AVD transition to VIH (90/100Mhz*)
0111 = Data is valid on the 11th active CLK edge after AVD transition to VIH (108/110Mhz*)
1000 = Data is valid on the 12th active CLK edge after AVD transition to VIH (120Mhz*)
1001 = Data is valid on the 13th active CLK edge after AVD transition to VIH (133Mhz*,default)
1010 = Data is valid on the 14th active CLK edge after AVD transition to VIH
1011 = Data is valid on the 15th active CLK edge after AVD transition to VIH
A13
A12
A11
Address Bit
Function
Settings(Binary)
A18
RDY Active
1 = RDY active one clock cycle before data
0 = RDY active with data(default)
A17
Burst Read Mode
000 = Continuous(default)
001 = 8-word linear with wrap
010 = 16-word linear with wrap
011~111 = Reserve
A16
A15
A14
Programmable Wait State
0000 = Data is valid on the 4th active CLK edge after AVD transition to VIH
0001 = Data is valid on the 5th active CLK edge after AVD transition to VIH (40Mhz*)
0010 = Data is valid on the 6th active CLK edge after AVD transition to VIH (50/54Mhz*)
0011 = Data is valid on the 7th active CLK edge after AVD transition to VIH (60/66Mhz*)
0100 = Data is valid on the 8th active CLK edge after AVD transition to VIH (70Mhz*)
0101 = Data is valid on the 9th active CLK edge after AVD transition to VIH (80/83Mhz*)
0110 = Data is valid on the 10th active CLK edge after AVD transition to VIH (90/100Mhz*)
0111 = Data is valid on the 11th active CLK edge after AVD transition to VIH (108/110Mhz*)
1000 = Data is valid on the 12th active CLK edge after AVD transition to VIH (120Mhz*)
1001 = Data is valid on the 13th active CLK edge after AVD transition to VIH (133Mhz*,default)
1010 = Data is valid on the 14th active CLK edge after AVD transition to VIH
1011 = Data is valid on the 15th active CLK edge after AVD transition to VIH
A13
A12
A11
Start
Addr.
Burst Address Sequence
Continuous Burst
8-word Burst
16-word Burst
Wrap
0
0-1-2-3-4-5-6...
0-1-2-3-4-5-6-7
0-1-2-3 ... -D-E-F
1
1-2-3-4-5-6-7...
1-2-3-4-5-6-7-0
1-2-3-4 ... -E-F-0
2
2-3-4-5-6-7-8...
2-3-4-5-6-7-0-1
2-3-4-5 ... -F-0-1
.