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參數(shù)資料
| 型號： | K8S5515ETC-SC1E0 |
| 元件分類： | PROM |
| 英文描述： | 16M X 16 FLASH 1.8V PROM, 100 ns, PBGA44 |
| 封裝： | 7.70 X 6.20 MM, 1 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, FBGA-44 |
| 文件頁數(shù)： | 10/65頁 |
| 文件大小： | 1196K |
| 代理商： | K8S5515ETC-SC1E0 |
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K8S5615ETC
datasheet NOR FLASH MEMORY
Rev. 1.0
this will enable the systems microprocessor to read the boot-up firmware from the Flash memory. If RESET is asserted during a program or erase opera-
tion, the device requires a time of tREADY (during Internal Routines) before the device is ready to read data again. If RESET is asserted when a program
or erase operation is not executing, the reset operation is completed within a time of tREADY (not during Internal Routines). tRH is needed to read data
after RESET returns to VIH. Refer to the AC Characteristics tables for RESET parameters and to Figure 12 for the timing diagram. When RESET is at
logic high, the device is in standard operation.
9.11 Software Reset
The reset command provides that the bank is reseted to read mode, erase-suspend-read mode or program-suspend-read mode. The addresses are in
Don’t Care state. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins, or in an pro-
gram command sequence before programming begins. If the device begins erasure or programming, the reset command is ignored until the operation is
completed. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the
erase-suspend-read mode. The reset command valid between the sequence cycles in an autoselect command sequence. In an autoselect mode, the
reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset
command returns that bank to the erase-suspend-read mode. Also, if a bank entered the autoselect mode while in the Program Suspend mode, writing
the reset command returns that bank to the program-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset com-
mand returns the banks to the read mode. (or erase-suspend-read mode if the bank was in Erase Suspend)
9.12 Program
The K8S(54/55/56/57)15E can be programmed in units of a word. Programming is writing 0's into the memory array by executing the Internal Program
Routine. In order to perform the Internal Program Routine, a four-cycle command sequence is necessary. The first two cycles are unlock cycles. The third
cycle is assigned for the program setup command. In the last cycle, the address of the memory location and the data to be programmed at that location
are written. The device automatically generates adequate program pulses and verifies the programmed cell margin by the Internal Program Routine. Dur-
ing the execution of the Routine, the system is not required to provide further controls or timings. During the Internal Program Routine, commands written
to the device will be ignored.
9.13 Accelerated Program
The device provides accelerated program operations through the Vpp input. Using this mode, faster manufacturing throughput at the factory is possible.
When VID is asserted on the Vpp input, the device automatically enters the Unlock Bypass mode, temporarily unprotects any protected blocks, and uses
the higher voltage on the input to reduce the time required for program operations. In accelerated program mode, the system would use a two-cycle pro-
gram command sequence for only a word program. By removing VID returns the device to normal operation mode.
Note that Read While Accelerated Program(Erase) and Program suspend(Erase suspend) mode are not guaranteed.
Program/Erase cycling must be limited below 100cycles for optimum performance.
Ambient temperature requirements : TA = 30°C±10°C
9.14 Write Buffer Programming
Write Buffer Programming allows the system write to a maximum of 32-word in one programming operation. This results in faster effective programming
time than the standard programming algorithms. The Write Buffer Programming command sequence is initi-ated by first writing two unlock cycles. This is
followed by a third write cycle containing the Write Buffer Load command written at the block address in which programming will occur. The fourth cycle
writes the block address and the number of word locations, minus one, to be programmed. For example, if the system will program 19 unique address
locations, then 12h should be written to the device. This tells the device how many write buffer addresses will be loaded with data. The number of loca-
tions to program cannot exceed the size of the write buffer or the operation will abort. The fifth cycle writes the first address location and data to be pro-
grammed. The write-buffer-page is selected by address bits A23(max.) ~ A5 entered at fifth cycle. All subsequent address/ data pairs must fall
within the selected write-buffer-page, so that all subsequent addresses must have the same address bit A23(max.) ~ A5 as those entered at
fifth cycle. Write buffer locations may be loaded in any order.
Once the specified number of write buffer locations have been loaded, the system must then write the "Program Buffer to Flash" com mand at the block
address. Any other command address/data combination aborts the Write Buffer Programming operation. The device then begins programming. Data poll-
ing should be used while monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5, and DQ1 should be monitored to determine
the device status during Write Buffer Programming. The write-buffer programming operation can be suspended using the standard program suspend/
resume commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to execute the next command.
Note also that an address loaction cannot be loaded more than once into the write-buffer-page.
The Write Buffer Programming Sequence can be aborted in the following ways:
Loading a value that is greater than the buffer size(32-word) during then number of word locations to Program step.
(In case, WC > 1FH @Table 8)
The number of Program address/data pairs entered is different to the number of word locations initially defined with WC (@Table 8)
Writing a Program address to have a different write-buffer-page with selected write-buffer-page
( Address bits A23(max) ~ A5 are different)
Writing non-exact "Program Buffer to Flash" command
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