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參數(shù)資料
| 型號： | K8S5515ETC-SC1E0 |
| 元件分類： | PROM |
| 英文描述： | 16M X 16 FLASH 1.8V PROM, 100 ns, PBGA44 |
| 封裝： | 7.70 X 6.20 MM, 1 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, FBGA-44 |
| 文件頁數(shù)： | 16/65頁 |
| 文件大?。?/td> | 1196K |
| 代理商： | K8S5515ETC-SC1E0 |
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K8S5615ETC
datasheet NOR FLASH MEMORY
Rev. 1.0
DQ5 : Exceed Timing Limits
If the Internal Program/Erase Routine extends beyond the timing limits, DQ5 will go High, indicating program/erase failure.
DQ3 : Block Erase Timer
The status of the multi-block erase operation can be detected via the DQ3 pin. DQ3 will go High if 50
μs of the block erase time window expires. In this
case, the Internal Erase Routine will initiate the erase operation.Therefore, the device will not accept further write commands until the erase operation is
completed. DQ3 is Low if the block erase time window is not expired. Within the block erase time window, an additional block erase command (30H) can
be accepted. To confirm that the block erase command has been accepted, the software may check the status of DQ3 following each block erase com-
mand.
DQ2 : Toggle Bit 2
The device generates a toggling pulse in DQ2 only if an Internal Erase Routine or an Erase/Program Suspend is in progress. When the device executes
the Internal Erase Routine, DQ2 toggles if the bank including an erasing block is read. Although the Internal Erase Routine is in the Exceeded Time Lim-
its, DQ2 toggles only if an erasing block in the Exceeded Time Limits is read. When the device is in the Erase/Program Suspend mode, DQ2 toggles only
if an address in the erasing or programming block is read. If a non-erasing or non-programmed block address is read during the Erase/Program Suspend
mode, then DQ2 will produce valid data. DQ2 will go High if the user tries to program a non-erase suspend block while the device is in the Erase Suspend
mode. #OE or #CE should be toggled in each toggle bit status read.
DQ1 : Buffer Program Abort Indicator
DQ1 indocates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a "1". The system must issue the Write-to-Buffer-
Abort-Reset command sequence to return the device to reading array data.
RDY: Ready
Normally the RDY signal is used to indicate if new burst data is available at the rising edge of the clock cycle or not. If RDY is low state, data is not valid
at expected time, and if high state, data is valid. Note that, if CE is low and OE is high, the RDY is high state.
Figure 1: Data Polling Algorithms
Figure 2: Toggle Bit Algorithms
Start
DQ7 = Data ?
No
DQ5 = 1 ?
Fail
Pass
Yes
DQ7 = Data ?
No
Yes
Read(DQ0~DQ7)
Valid Address
Read(DQ0~DQ7)
Valid Address
Start
DQ6 = Toggle ?
No
DQ5 = 1 ?
Fail
Pass
No
DQ6 = Toggle ?
Yes
No
Read twice(DQ0~DQ7)
Valid Address
Read(DQ0~DQ7)
Valid Address
Yes
Read(DQ0~DQ7)
Valid Address
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