參數(shù)資料
型號(hào)： ISP1761BE,551
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝： 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128
文件頁數(shù)： 16/164頁
文件大小： 767K
代理商： ISP1761BE,551
ISP1761_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
111 of 163
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
[1]
The reserved bits should always be written with the reset value.
Table 112. Control Function register (address 0228h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
reserved[1]
CLBUF
VENDP
DSEN
STATUS
STALL
Reset
00000000
Bus reset
00000000
Access
R/W
W
R/W
Table 113. Control Function register (address 0228h) bit description
Bit
Symbol
Description
7 to 5 -
reserved
4
CLBUF
Clear Buffer: Logic 1 clears the RX buffer of the indexed endpoint; the TX
buffer is not affected. The RX buffer is automatically cleared once the endpoint
is completely read. This bit is set only when it is necessary to forcefully clear
the buffer.
Remark: If using double buffer, to clear both the buffers issue the CLBUF
command two times, that is, set and clear this bit two times.
3
VENDP
Validate Endpoint: Logic 1 validates data in the TX FIFO of an IN endpoint for
sending on the next IN token. In general, the endpoint is automatically validated
when its FIFO byte count has reached the endpoint MaxPacketSize. This bit is
set only when it is necessary to validate the endpoint with the FIFO byte count
that is below the Endpoint MaxPacketSize.
2
DSEN
Data Stage Enable: This bit controls the response of the ISP1761 to a control
transfer. After the completion of the set-up stage, rmware must determine
whether a data stage is required. For control OUT, rmware will set this bit and
the ISP1761 goes into the data stage. Otherwise, the ISP1761 will NAK the
data stage transfer. For control IN, rmware will set this bit before writing data to
the TX FIFO and validate the endpoint. If no data stage is required, rmware
can immediately set the STATUS bit after the set-up stage.
Remark: The DSEN bit is cleared once the OUT token is acknowledged by the
device and the IN token is acknowledged by the PC host. This bit cannot be
read back and reading this bit will return logic 0.
1
STATUS
Status Acknowledge: Only applicable for control IN and OUT.
This bit controls the generation of ACK or NAK during the status stage of a
SETUP transfer. It is automatically cleared when the status stage is completed
and a SETUP token is received. No interrupt signal will be generated.
0 — Sends NAK
1 — Sends an empty packet following the IN token (peripheral-to-host) or ACK
following the OUT token (host-to-peripheral)
Remark: The STATUS bit is cleared to zero once the zero-length packet is
acknowledged by the device or the PC host.
Remark: Data transfers preceding the status stage must rst be fully completed
before the STATUS bit can be set.
0
STALL
Stall Endpoint: Logic 1 stalls the indexed endpoint. This bit is not applicable for
isochronous transfers.
Remark: Stalling a data endpoint will confuse the Data Toggle bit about the
stalled endpoint because the internal logic picks up from where it is stalled.
Therefore, the Data Toggle bit must be reset by disabling and re-enabling the
corresponding endpoint (by setting bit ENABLE to logic 0, followed by logic 1 in
the Endpoint Type register) to reset the PID.
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