參數(shù)資料
型號: ISP1761BE,551
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128
文件頁數(shù): 106/164頁
文件大小: 767K
代理商: ISP1761BE,551
ISP1761_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
45 of 163
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
8.3.2 HcChipID register
Read this register to get the ID of the ISP1761. This upper word of the register contains
the hardware version number and the lower word contains the chip ID. Table 36 shows the
bit description of the register.
8.3.3 HcScratch register
This register is for testing and debugging purposes only. The value read back must be the
same as the value that was written. The bit description of this register is given in Table 37.
8.3.4 SW Reset register
Table 38 shows the bit allocation of the register.
2
INTR_POL
Interrupt Polarity:
0 — Active LOW
1 — Active HIGH
1
INTR_LEVEL
Interrupt Level:
0 — INT is level triggered.
1 — INT is edge triggered. A pulse of certain width is generated.
0
GLOBAL_INTR_EN
Global Interrupt Enable: This bit must be set to logic 1 to enable
IRQ signal assertion.
0 — IRQ assertion disabled. IRQ will never be asserted,
regardless of other settings or IRQ events.
1 — IRQ assertion enabled. IRQ will be asserted according to the
HcInterruptEnable register, and events setting and occurrence.
Table 35.
HW Mode Control - Hardware Mode Control register (address 0300h) bit
description …continued
Bit
Symbol
Description
Table 36.
HcChipID - Host Controller Chip Identier register (address 0304h) bit description
Bit
Symbol
Access
Value
Description
31 to 0
CHIPID[31:0]
R
0001 1761h
Chip ID: This register represents the hardware version number
(0001h) and the chip ID (1761h) for the host controller.
Table 37.
HcScratch - Host Controller Scratch register (address 0308h) bit description
Bit
Symbol
Access
Value
Description
31 to 0
SCRATCH[31:0]
R/W
0000 0000h
Scratch: For testing and debugging purposes
Table 38.
SW Reset - Software Reset register (address 030Ch) bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
reserved[1]
Reset
00000000
Access
R/W
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