參數(shù)資料
型號： ISP1761BE,551
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝： 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128
文件頁數(shù)： 135/164頁
文件大?。?/td> 767K
代理商： ISP1761BE,551
ISP1761_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
71 of 163
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
DW3
63
A
HW — writes
SW — writes
-
Active: Write the same value as that in V.
62
H
HW — writes
-
Halt: Transaction is halted.
61 to 58 reserved
-
57
DT
HW — writes
SW — writes
-
Data Toggle: Set the Data Toggle bit to start the PTD. Software
writes the current transaction toggle value. Hardware writes the next
transaction toggle value.
56 to 55 Cerr[1:0]
HW — writes
SW — writes
-
Error Counter: This eld corresponds to the Cerr[1:0] eld in TD. The
default value of this eld is zero for isochronous transactions.
54 to 47 reserved
-
46 to 32 NrBytes
Transferred
[14:0]
HW — writes
-
Number of Bytes Transferred: This eld indicates the number of
bytes sent or received for this transaction. If Mult[1:0] is greater than
one, it is possible to store intermediate results in this eld.
DW2
31 to 24 reserved
-
23 to 8
DataStart
Address[15:0]
SW — writes
-
Data Start Address: This is the start address for data that will be
sent or received on or from the USB bus. This is the internal memory
address and not the direct CPU address.
RAM address = (CPU address
400h) / 8
7to0
Frame[7:0]
SW — writes
-
Bits 7 to 3 represent the polling rate in milliseconds.
The INT polling rate is dened as 2(b - 1)
SOF, where b is 1 to 9.
When b is 1, 2, 3 or 4, use
SA to dene polling because the rate is
equal to or less than 1 ms. Bits 7 to 3 are set to 0. Polling checks
SA
bits for
SOF rates. See Table 69.
DW1
63 to 47 reserved
-
46
S
SW — writes
-
This bit indicates if a split transaction has to be executed:
0 — High-speed transaction
1 — Split transaction
45 to 44 EPType[1:0]
SW — writes
-
Endpoint type:
11 — Interrupt
43 to 42 Token[1:0]
SW — writes
-
Token: This eld indicates the token PID for this transaction:
00 — OUT
01 — IN
41 to 35 DeviceAddress
[6:0]
SW — writes
-
Device Address: This is the USB address of the function containing
the endpoint that is referred to by the buffer.
34 to 32 EndPt[3:1]
SW — writes
-
Endpoint: This is the USB address of the endpoint within the
function.
DW0
31
EndPt[0]
SW — writes
-
Endpoint: This is the USB address of the endpoint within the
function.
Table 68.
High-speed interrupt IN and OUT: bit description …continued
Bit
Symbol
Access
Value Description
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