參數(shù)資料
型號(hào): ISP1761BE,551
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128
文件頁數(shù): 117/164頁
文件大?。?/td> 767K
代理商: ISP1761BE,551
ISP1761_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
55 of 163
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
8.4.2 HcInterruptEnable register
This register allows enabling or disabling of the IRQ generation because of various events
as described in Table 55.
5
HCSUSP
Host Controller Suspend: Indicates that the host controller has
entered suspend mode. The IRQ line will be asserted if the respective
enable bit in the HcInterruptEnable register is set.
0 — The host controller did not enter suspend mode.
1 — The host controller entered suspend mode.
If the Interrupt Service Routine (ISR) accesses the ISP1761, it will wake
up for the time specied in bits 31 to 16 of the Power Down Control
register.
4
-
reserved; write reset value
3
DMAEOTINT
DMA EOT Interrupt: Indicates the DMA transfer completion. The IRQ
line will be asserted if the respective enable bit in the HcInterruptEnable
register is set.
0 — No DMA transfer is completed
1 — DMA transfer is completed
2
-
reserved; write reset value; value is zero just after reset and changes to
one after a short while
1
SOFITLINT
SOT ITL Interrupt: The IRQ line will be asserted if the respective
enable bit in the HcInterruptEnable register is set.
0 — No SOF event has occurred
1 — An SOF event has occurred
0
-
reserved; write reset value; value is zero just after reset and changes to
one after a short while
Table 54.
HcInterrupt - Host Controller Interrupt register (address 0310h) bit
description …continued
Bit
Symbol
Description
Table 55.
HcInterruptEnable - Host Controller Interrupt Enable register (address 0314h) bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved[1]
OTG_IRQ_
E
ISO_IRQ_E
ATL_IRQ
_E
Reset
00000000
Access
R/W
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