參數(shù)資料
型號： ISP1761BE,551
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝： 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128
文件頁數(shù)： 147/164頁
文件大?。?/td> 767K
代理商： ISP1761BE,551
ISP1761_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
82 of 163
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
Table 76.
Start and complete split for interrupt: bit description
Bit
Symbol
Access
Value Description
DW7
63 to 40
reserved
-
39 to 32
INT_IN_7[7:0]
HW — writes
-
Bytes received during
SOF7, if SA[7] is set to 1 and frame number is
correct. The new value continuously overwrites the old value.
DW6
31 to 24
INT_IN_6[7:0]
HW — writes
-
Bytes received during
SOF6, if SA[6] is set to 1 and frame number is
correct. The new value continuously overwrites the old value.
23 to 16
INT_IN_5[7:0]
HW — writes
-
Bytes received during
SOF5, if SA[5] is set to 1 and frame number is
correct. The new value continuously overwrites the old value.
15 to 8
INT_IN_4[7:0]
HW — writes
-
Bytes received during
SOF4, if SA[4] is set to 1 and frame number is
correct. The new value continuously overwrites the old value.
7 to 0
INT_IN_3[7:0]
HW — writes
-
Bytes received during
SOF3, if SA[3] is set to 1 and frame number is
correct. The new value continuously overwrites the old value.
DW5
63 to 56
INT_IN_2[7:0]
HW — writes
-
Bytes received during
SOF2 (bits 7 to 0), if SA[2] is set to 1 and
frame number is correct. The new value continuously overwrites the
old value.
55 to 48
INT_IN_1[7:0]
HW — writes
-
Bytes received during
SOF1, if SA[1] is set to 1 and frame number is
correct. The new value continuously overwrites the old value.
47 to 40
INT_IN_0[7:0]
HW — writes
-
Bytes received during
SOF0 if SA[0] is set to 1 and frame number is
correct. The new value continuously overwrites the old value.
39 to 32
SCS[7:0]
SW — writes
(0
→ 1)
HW — writes
(1
→ 0)
After
processing
-
All bits can be set to one for every transfer. It species which
SOF the
complete split needs to be sent. Valid only for IN. Start split and
complete split active bits,
SA = 0000 0001 and SCS = 0000 0100,
will cause SS to execute in
Frame0 and CS in Frame2.
DW4
31 to 29
Status7[2:0]
HW — writes
-
Interrupt IN or OUT status of
SOF7
28 to 26
Status6[2:0]
HW — writes
-
Interrupt IN or OUT status of
SOF6
25 to 23
Status5[2:0]
HW — writes
-
Interrupt IN or OUT status of
SOF5
22 to 20
Status4[2:0]
HW — writes
-
Interrupt IN or OUT status of
SOF4
19 to 17
Status3[2:0]
HW — writes
-
Interrupt IN or OUT status of
SOF3
16 to 14
Status2[2:0]
HW — writes
-
Interrupt IN or OUT status of
SOF2
13 to 11
Status1[2:0]
HW — writes
-
Interrupt IN or OUT status of
SOF1
10 to 8
Status0[2:0]
HW — writes
-
Interrupt IN or OUT status of
SOF0
Bit 0 — Transaction error (IN and OUT)
Bit 1 — Babble (IN token only)
Bit 2 — Underrun (OUT token only)
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