參數(shù)資料
型號: ISP1581BD
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Universal Serial Bus 2.0 high-speed interface device
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 38/73頁
文件大?。?/td> 1819K
代理商: ISP1581BD
Philips Semiconductors
ISP1581
USB 2.0 HS interface device
Objective specification
Rev. 02 — 23 October 2000
38 of 73
9397 750 07648
Philips Electronics N.V. 2000. All rights reserved.
9.5.2
Chip ID register (address: 70H)
This read-only register contains the chip identification and the hardware version
numbers. The firmware should check this information to determine the functions and
features supported. The register contains 3 bytes and the bit allocation is shown in
Table 60
.
22
21
20
19
18
17
16
15
14
13
12
11
EP6RX
EP5TX
EP5RX
EP4TX
EP4RX
EP3TX
EP3RX
EP2TX
EP2RX
EP1TX
EP1RX
EP0TX
A logic 1 indicates the Endpoint 6 RX buffer as interrupt source.
A logic 1 indicates the Endpoint 5 TX buffer as interrupt source.
A logic 1 indicates the Endpoint 5 RX buffer as interrupt source.
A logic 1 indicates the Endpoint 4 TX buffer as interrupt source.
A logic 1 indicates the Endpoint 4 RX buffer as interrupt source.
A logic 1 indicates the Endpoint 3 TX buffer as interrupt source.
A logic 1 indicates the Endpoint 3 RX buffer as interrupt source.
A logic 1 indicates the Endpoint 2 TX buffer as interrupt source.
A logic 1 indicates the Endpoint 2 RX buffer as interrupt source.
A logic 1 indicates the Endpoint 1 TX buffer as interrupt source.
A logic 1 indicates the Endpoint 1 RX buffer as interrupt source.
A logic 1 indicates the Endpoint 0 data TX buffer as interrupt
source.
A logic 1 indicates the Endpoint 0 data RX buffer as interrupt
source.
reserved.
A logic 1 indicates that a SETUP token was received on
Endpoint 0.
reserved.
DMA status:
A logic 1 indicates a change in the DMA Status
register.
High Speed Status:
.A logic 1 indicates a change from FS to
HS mode (HS connection). This bit is not set, when the system
goes into a FS suspend.
Resume status:
A logic 1 indicates that a status change from
‘suspend’ to ‘resume’ (active) was detected.
Suspend status:
A logic 1 indicates that a status change from
active to ‘suspend’ was detected on the bus.
Pseudo SOF interrupt:
A logic 1 indicates that a Pseudo SOF
or
μ
SOF was received. Pseudo SOF is an internally generated
clock signal (FS: 1 ms period, HS: 125
μ
s period) synchronized
to the USB bus SOF/
μ
SOF.
SOF interrupt:
A logic 1 indicates that a SOF/
μ
SOF was
received.
Bus Reset
: A logic 1 indicates that a USB bus reset was
detected.
10
EP0RX
9
8
reserved
EP0SETUP
7
6
reserved
DMA
5
HS_STAT
4
RESUME
3
SUSP
2
PSOF
1
SOF
0
BRESET
Table 59: Interrupt register: bit description
…continued
Bit
Symbol
Description
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