參數(shù)資料
型號(hào)： ISP1581BD
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Universal Serial Bus 2.0 high-speed interface device
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁(yè)數(shù)： 10/73頁(yè)
文件大小： 1819K
代理商： ISP1581BD
Philips Semiconductors
ISP1581
USB 2.0 HS interface device
Objective specification
Rev. 02 — 23 October 2000
10 of 73
9397 750 07648
Philips Electronics N.V. 2000. All rights reserved.
7.8 Microcontroller Interface and Microcontroller Handler
The Microcontroller Interface allows direct interfacing to most microcontrollers. The
interface is configured at power-up via inputs BUS_CONF, MODE1 and MODE0.
When BUS_CONF is set to logic 1, the Microcontroller Interface switches to the
Generic Processor mode
in which AD[7:0] is the 8-bit address bus and DATA[15:0]
is the separate 16-bit data bus. If BUS_CONF is made logic 0, the interface is in the
Split Bus mode
, where AD[7:0] is the local microprocessor bus (multiplexed
address/data) and DATA[15:0] is used as the DMA bus.
If pin MODE0 is set to logic 1, pins RD and WR are the read and write strobes (8051
style). If pin MODE0 is logic 0, pins R/W and DS pins represent the direction and data
strobe (Motorola style).
When pin MODE1 is made logic 0, ALE is used to latch the multiplexed address on
pins AD[7:0]. If pin MODE1 is set to logic 1, A0 is used to indicate address or data.
Pin MODE1 is only used in Split Bus mode: in Generic Processor mode it must be
tied to V
CC(5.0)
(logic 1).
The Microcontroller Handler allows the external microcontroller to access the register
set in the Philips SIE as well as the DMA Handler. The initialization of the DMA
configuration is done via the Microcontroller Handler.
7.9 DMA Interface and DMA Handler
The DMA block can be subdivided into two blocks: the DMA Handler and the DMA
Interface.
The firmware writes to the DMA Command register to start a DMA transfer (see
Table 30
). The command opcode determines whether a generic DMA, PIO, MDMA or
UDMA transfer will start. The Handler interfaces to the same FIFO (internal RAM) as
used by the USB core. Upon receiving the DMA Command, the DMA Handler directs
the data from the internal RAM to the external DMA device and vice versa.
The DMA Interface configures the timings and how the DMA data is accessed. Data
can be transferred either using DIOR and DIOW strobes or by the DACK and DREQ
handshakes. The different DMA configurations are set up by writing to the DMA
Configuration register (see
Table 35
).
For an IDE-based storage interface, the applicable DMA modes are PIO (Parallel
I/O), MDMA (Multiword DMA; ATA), and UDMA (Ultra DMA; ATA).
For a generic DMA interface, the DMA modes that can be used are Generic DMA
(Slave) and MDMA (Master).
7.10 System Controller
The System Controller implements the USB power-down capabilities of the ISP1581.
Two modes are supported during ‘suspend’ state:
powered-on
and
powered-off
.
These modes are selected via bit PWROFF in the Mode register (see
Table 7
).
Registers are protected against data corruption during wake-up following a ‘resume’.
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