參數(shù)資料
型號(hào)： ISP1581BD
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Universal Serial Bus 2.0 high-speed interface device
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁(yè)數(shù)： 19/73頁(yè)
文件大?。?/td> 1819K
代理商： ISP1581BD
Philips Semiconductors
ISP1581
USB 2.0 HS interface device
Objective specification
Rev. 02 — 23 October 2000
19 of 73
9397 750 07648
Philips Electronics N.V. 2000. All rights reserved.
9.3.2
Control Function register (address: 28H)
The Control Function register is used to perform the buffer management on the
endpoints. It consists of 1 byte and the bit configuration is given in
Table 17
.The
register bits can stall, clear or validate any enabled data endpoint. Before accessing
this register, the Endpoint Index register must be written first to specify the target
endpoint.
[1]
Only applicable for Endpoint 0.
9.3.3
Data Port register (address: 20H)
This 2-byte register provides direct access for a microcontroller to the FIFO of the
indexed endpoint. In case of an 8-bit bus the upper byte is not used. The bit allocation
is shown in
Table 19
.
Device to host (IN endpoint):
After each write action an internal counter is
auto-incremented (by 2 for a 16-bit access, by 1 for an 8-bit access) to the next
location in the TX FIFO. When all bytes have been written, the buffer can be validated
via the Control Function register (bit VENDP). The data packet will then be sent on
the next IN token.
Table 17: Control Function register: bit allocation
Bit
7
Symbol
reserved
Reset
0
Bus reset
0
Access
R/W
6
5
4
3
2
1
0
reserved
0
0
R/W
reserved
0
0
R/W
CLBUF
0
0
R/W
VENDP
0
0
R/W
reserved
0
0
R/W
STATUS
[1]
0
0
R/W
STALL
0
0
R/W
Table 18: Control Function register: bit description
Bit
Symbol
7 to 5
-
4
CLBUF
Description
reserved.
Clear Buffer:
A logic 1 clears the RX buffer of the indexed
endpoint; the TX buffer is not affected. Before new data can be
received, old data in the buffer must be cleared first.
Validate Endpoint:
A logic 1 validates the data in the TX FIFO
of an IN endpoint for sending on the next IN token. The FIFO
byte count is below or equal to the Endpoint MaxPacketSize.
reserved
Status Acknowledge:
This bit controls the generation of ACK
or NAK during the status stage of a SETUP packet. It is
automatically cleared upon completion of the status stage and
upon receiving a SETUP token.
0 —
sends NAK
1 —
sends empty packet following IN token (host-to-device) or
ACK following OUT token (device-to-host).
Stall Endpoint
: A logic 1 stalls the indexed endpoint. This bit is
not applicable for isochronous transfers.
3
VENDP
2
1
-
STATUS
0
STALL
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