參數(shù)資料
型號： ISP1581BD
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Universal Serial Bus 2.0 high-speed interface device
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù)： 24/73頁
文件大小： 1819K
代理商： ISP1581BD
Philips Semiconductors
ISP1581
USB 2.0 HS interface device
Objective specification
Rev. 02 — 23 October 2000
24 of 73
9397 750 07648
Philips Electronics N.V. 2000. All rights reserved.
9.4 DMA registers
Two types of Generic DMA transfer and three types of IDE-specified transfer can be
done by writing the proper opcode in the DMA Command Register. The control bits
are given in
Table 28
(Generic DMA transfers) and
Table 29
(IDE-specified transfers).
GDMA read/write (opcode = 00H/01H) —
Generic DMA Slave mode; the DIOR and
DIOW strobe signals are driven by the external DMA Controller.
MDMA (Master) read/write (opcode = 06H/07H) —
Generic DMA Master mode; the
DIOR and DIOW strobe signals are driven by the ISP1581.
PIO read/write (opcode = 04H/05H) —
PIO mode for IDE transfers; the specification
of this mode can be obtained from the ATA Specification Rev. 4 DIOR and DIOW are
used as data strobes, IORDY can be used by the device to extend the PIO cycle.
MDMA read/write (opcode = 06H/07H) —
Multiword DMA mode for IDE transfers;
the specification of this mode can be obtained from the ATA Specification Rev. 4
DIOR and DIOW are used as data strobes, while DREQ and DACK serve as
handshake signals.
UDMA read/write (opcode = 02H/03H) —
Ultra DMA mode for IDE transfers; the
specification of this mode can be obtained from the ATA Specification Rev. 4 Pins
DA0 to DA2, CS0 and CS1 are used to select a device register for access. Control
signals are mapped as follows: DREQ (= DMARQ), DACK (= DMACK), DIOW
(= STOP), DIOR (= HDMARDY or HSTROBE), IORDY (= DSTROBE or DDMARDY).
Table 28: Control bits for Generic DMA transfers
Control bits
GDMA read/write (opcode = 00H/01H)
DMA Configuration register (see
Table 35
)
BURST[2:0]
Description
determines the number of DMA cycles during which pin
DREQ is kept asserted
determines the active data strobe(s)
selects the DMA bus width: 8 or 16 bits
disables the use of the DMA Transfer Counter
set to logic 0 (non-ATA transfer)
MODE[1:0]
WIDTH0
DIS_XFER_CNT
ATA_MODE
DMA Hardware register (see
Table 37
)
EOT_POL
ACK_POL, DREQ_POL,
WRITE_POL, READ_POL
MASTER
selects the polarity of the EOT signal
select the polarity of the DMA handshake signals
set to logic 0 (slave)
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