參數(shù)資料
型號(hào)： ISP1183BS,157
廠商： ST-ERICSSON
元件分類(lèi)： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQCC32
封裝： 5 X 5 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-617-1, HVQFN-32
文件頁(yè)數(shù)： 64/65頁(yè)
文件大?。?/td> 306K
代理商： ISP1183BS,157
ISP1183_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 7 June 2007
8 of 65
NXP Semiconductors
ISP1183
Low-power USB Peripheral Controller with DMA
7.5 Bit clock recovery
The bit clock recovery circuit recovers the clock from the incoming USB data stream using
a 4
× over-sampling principle. It can track jitter and frequency drift as specied in
Universal Serial Bus Specication Rev. 2.0.
7.6 Voltage regulator
A 5 V-to-3.3 V voltage regulator is integrated on-chip to supply the analog transceiver and
internal logic. This voltage is available at pin VREG(3V3) to supply an external 1.5 k pull-up
resistor on pin DP. Alternatively, the ISP1183 provides the SoftConnect technology
through an integrated 1.5 k
pull-up resistor (see Section 7.4).
7.7 PLL clock multiplier
A 6 MHz-to-48 MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip. This
allows for the use of a low-cost 6 MHz crystal, which also minimizes EMI. No external
components are required for the operation of the PLL.
7.8 PIO and DMA interfaces
A generic Parallel I/O (PIO) interface is dened for speed and ease-of-use. It also allows
direct interfacing to most microcontrollers. To a microcontroller, the ISP1183 appears as a
memory device with an 8-bit data bus and a 1-bit address bus. The ISP1183 supports
non-multiplexed address and data buses.
The ISP1183 can also be congured as a Direct Memory Access (DMA) slave device to
allow more efcient data transfer. One of the 14 endpoint FIFOs may directly transfer data
to or from the local shared memory. The DMA interface can independently be congured
from the PIO interface.
It can be directly interfaced to microprocessors or microcontrollers with an I/O supply
voltage as low as 1.65 V.
7.9 VBUS indicator
The ISP1183 indicates the availability of VBUS using the VBUS pin. When VBUS is available
(at pin VBUS), pin VBUSDET_N will output LOW. When VBUS is not available (at pin VBUS),
pin VBUSDET_N will output HIGH. Pin VBUSDET_N will change from HIGH-to-LOW level
in approximately 2.5 ms to 3.5 ms. See Section 17.
7.10 Operation modes
The ISP1183 can be operated in several operation modes as given in Table 3.
Table 3.
ISP1183 operation modes
Pin name
Plug-out state Dead state
Reset state
Plug-in state
Normal state
VBUS
0V
X
5 V
VDD(I/O)
1.8 V
0 V
1.8 V
WAKEUP
X
L
RESET_N
X
L
H
INT_N
H
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ISP1183BS-T 功能描述:USB 接口集成電路 FULL-SPD USB2 DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類(lèi)型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
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ISP1183PC 制造商:ST-Ericsson 功能描述:Low Power Universal Serial Bus Peripheral Controller w/ DMA
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