參數(shù)資料
型號(hào)： ISP1183BS,157
廠商： ST-ERICSSON
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQCC32
封裝： 5 X 5 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-617-1, HVQFN-32
文件頁(yè)數(shù)： 14/65頁(yè)
文件大?。?/td> 306K
代理商： ISP1183BS,157
ISP1183_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 7 June 2007
21 of 65
NXP Semiconductors
ISP1183
Low-power USB Peripheral Controller with DMA
11. Suspend and resume
11.1 Suspend conditions
The ISP1183 detects a USB suspend status when a constant idle state is present on the
USB bus for more than 3 ms.
The bus-powered devices that are suspended must not consume more than 500
A of
current. This is achieved by shutting down power to system components or supplying
them with a reduced voltage.
The steps leading up to the suspend status are:
1. On detecting a wake-up-to-suspend transition, the ISP1183 sets bit SUSPND in the
Interrupt register. This will generate an interrupt if bit IESUSP in the Interrupt Enable
register is set.
2. When rmware detects a suspend condition, it must prepare all system components
for the suspend state:
a. All signals connected to the ISP1183 must enter appropriate states to meet the
power consumption requirements of the suspend state.
b. All input pins of the ISP1183 must have a CMOS LOW or HIGH level.
3. In the interrupt service routine, rmware must check the current status of the USB
bus. When bit BUSTATUS in the Interrupt register is logic 0, the USB bus has left
suspend mode and the process must be aborted. Otherwise, the next step can be
executed.
4. To meet suspend current requirements for a bus-powered device, internal clocks must
be switched off by clearing bit CLKRUN in the Hardware Conguration register.
5. When rmware has set and cleared bit GOSUSP in the Mode register, the ISP1183
enters the suspend state. In powered-off application, the ISP1183 asserts output
SUSPEND and switches off internal clocks after 2 ms.
Figure 11 shows a typical timing diagram.
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