參數(shù)資料
型號(hào)： ISP1183BS,157
廠商： ST-ERICSSON
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQCC32
封裝： 5 X 5 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-617-1, HVQFN-32
文件頁數(shù)： 4/65頁
文件大小： 306K
代理商： ISP1183BS,157
ISP1183_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 7 June 2007
12 of 65
NXP Semiconductors
ISP1183
Low-power USB Peripheral Controller with DMA
Bits SUSPND, RESET, RESUME, SP_EOT, EOT and SOF are cleared when the Interrupt
register is read. The endpoint bits (EP0OUT to EP14) are cleared when the associated
Endpoint Status register is read.
Bit BUSTATUS follows the USB bus status exactly, allowing rmware to get the current
bus status when reading the Interrupt register.
SETUP and OUT token interrupts are generated after the ISP1183 has acknowledged the
associated data packet. In bulk transfer mode, the ISP1183 will issue interrupts for every
ACK received for an OUT token or transmitted for an IN token.
In isochronous mode, an interrupt is issued on each packet transaction. Firmware is
responsible for timing synchronization with the host. This can be done using the Pseudo
Start-Of-Frame (PSOF) interrupt, enabled using bit IEPSOF in the Interrupt Enable
register. If a Start-Of-Frame (SOF) is lost, PSOF interrupts are generated every 1 ms. This
allows rmware to keep data transfer synchronized with the host. After three missed SOF
events, the ISP1183 will enter the suspend state.
An alternative way of handling the isochronous data transfer is to enable both the SOF
and PSOF interrupts, and disable the interrupt for each isochronous endpoint.
Fig 8.
Interrupt logic
004aaa255
IERST
Interrupt
Enable register
IESUSP
IERESM
IESOF
IEP14
...
IEP0IN
IEP0OUT
Device Mode
register
INTENA
INTLVL
Hardware Configuration
register
PULSE
GENERATOR
INT_N
1
0
.
Interrupt register
RESET
SUSPND
RESUME
SOF
EP14
...
EP0IN
EP0OUT
RESET
reset interrupt source
suspend interrupt source
EPn interrupt source
(clear EPn interrupt; reading EPn
Status register will set this signal)
(clear SUSPEND interrupt; reading
Interrupt register will set this signal)
(clear RESET interrupt; reading
Interrupt register will set this signal)
.
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