參數(shù)資料
型號(hào): ISP1183BS,157
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC32
封裝: 5 X 5 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-617-1, HVQFN-32
文件頁(yè)數(shù): 31/65頁(yè)
文件大?。?/td> 306K
代理商: ISP1183BS,157
ISP1183_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 7 June 2007
37 of 65
NXP Semiconductors
ISP1183
Low-power USB Peripheral Controller with DMA
The internal DMA counter is automatically reloaded from the DMA Counter register when
DMA is re-enabled (DMAEN = 1). For details, see Section 12.3.2.
Code: F2h/F3h — write or read DMA Counter register
Transaction — write or read 2 bytes
12.4 General commands
12.4.1 Endpoint Error Code (R: A0h to AFh)
This command returns the status of the last transaction of the selected endpoint, as
stored in the Error Code register. Each new transaction overwrites the previous status
information. The bit allocation of the Error Code register is shown in Table 36.
Code: A0h to AFh — read error code (control OUT, control IN, endpoints 1 to 14)
Transaction — read 1 byte
Table 34.
DMA Counter register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
DMACRH[7:0]
Reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
DMACRL[7:0]
Reset
00000000
Access
R/W
Table 35.
DMA Counter register: bit description
Bit
Symbol
Description
15 to 8
DMACRH[7:0]
DMA Counter register (high byte)
7 to 0
DMACRL[7:0]
DMA Counter register (low byte)
Table 36.
Error Code register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
UNREAD
DATA01
reserved
ERROR[3:0]
RTOK
Reset
00000000
Access
RRRRRRRR
Table 37.
Error Code register: bit description
Bit
Symbol
Description
7
UNREAD
Logic 1 indicates that a new event occurred before the previous status
was read.
6
DATA01
This bit indicates the PID type of the last successfully received or
transmitted packet (0 = DATA0 PID, 1 = DATA1 PID).
5
-
reserved
4 to 1
ERROR[3:0]
Error code. For error description, see Table 38.
0
RTOK
Logic 1 indicates that data was successfully received or transmitted.
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