參數(shù)資料
型號: ISP1183BS,157
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC32
封裝: 5 X 5 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-617-1, HVQFN-32
文件頁數(shù): 27/65頁
文件大?。?/td> 306K
代理商: ISP1183BS,157
ISP1183_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 7 June 2007
33 of 65
NXP Semiconductors
ISP1183
Low-power USB Peripheral Controller with DMA
12.2.3 Stall or Unstall Endpoint (40h to 4Fh/80h to 8Fh)
These commands are used to stall or unstall an endpoint. The commands modify the
content of the Endpoint Status register (see Table 26).
A stalled control endpoint is automatically unstalled when it receives a SETUP token,
regardless of the packet content. If the endpoint should stay in its stalled state, the
microcontroller can re-stall it with the Stall Endpoint command.
When a stalled endpoint is unstalled (either by the Unstall Endpoint command or by
receiving a SETUP token), it is also re-initialized. This ushes the buffer: if it is an OUT
buffer, it waits for a DATA0 PID; if it is an IN buffer, it writes a DATA0 PID.
Code: 40h to 4Fh — stall (control OUT, control IN, endpoints 1 to 14)
Code: 80h to 8Fh — unstall (control OUT, control IN, endpoints 1 to 14)
Transaction — none
Remark: When unstalling a stalled endpoint, issue the unstall command two times. The
rst unstall command will update the Endpoint Status register in RAM. The second unstall
command will reset buffer pointers.
12.2.4 Validate Endpoint Buffer (61h to 6Fh)
This command signals the presence of valid data for transmission to the USB host, by
setting the Buffer Full ag of the selected IN endpoint. This indicates that the data in the
buffer is valid and can be sent to the host, when the next IN token is received. For a
double-buffered endpoint, this command switches the current FIFO for CPU access.
Remark: For special aspects of the control IN endpoint, see Section 9.5.
Table 27.
Endpoint Status register: bit description
Bit
Symbol
Description
7
EPSTAL
This bit indicates whether the endpoint is stalled or not (1 = stalled, 0 = not
stalled).
Set by a Stall Endpoint command. Cleared by an Unstall Endpoint
command. The endpoint is automatically unstalled on receiving a SETUP
token.
6
EPFULL1
Logic 1 indicates that the secondary endpoint buffer is full.
5
EPFULL0
Logic 1 indicates that the primary endpoint buffer is full.
4
DATA_PID
This bit indicates the data PID of the next packet (0 = DATA0 PID, 1 =
DATA1 PID).
3
OVERWRITE
This bit is set by hardware. Logic 1 indicates that a new set-up packet has
overwritten the previous set-up information, before it was acknowledged or
before the endpoint was stalled. This bit is cleared by reading, if writing the
set-up data has nished.
Firmware must check this bit before sending an Acknowledge Setup
command or stalling the endpoint. On reading logic 1, rmware must stop
ongoing set-up actions and wait for a new set-up packet.
2
SETUPT
Logic 1 indicates that the buffer contains a set-up packet.
1
CPUBUF
This bit indicates which buffer is currently selected for CPU access (0 =
primary buffer, 1 = secondary buffer).
0
-
reserved
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