參數(shù)資料
型號: ISP1183BS,157
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC32
封裝: 5 X 5 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-617-1, HVQFN-32
文件頁數(shù): 18/65頁
文件大小: 306K
代理商: ISP1183BS,157
ISP1183_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 7 June 2007
25 of 65
NXP Semiconductors
ISP1183
Low-power USB Peripheral Controller with DMA
Data ow commands
Write Control OUT Buffer
illegal: endpoint is
read-only
(00h)
-
Write Control IN Buffer
FIFO endpoint 0 IN
01h
N
≤ 64 bytes
Write Endpoint n Buffer (n =
1 to 14)
FIFO endpoints 1 to 14 (IN
endpoints only)
02h to 0Fh
isochronous: N
1023 bytes
interrupt or bulk:
N
≤ 64 bytes
Read Control OUT Buffer
FIFO endpoint 0 OUT
10h
N
≤ 64 bytes
Read Control IN Buffer
illegal: endpoint is
write-only
(11h)
-
Read Endpoint n Buffer (n =
1 to 14)
FIFO endpoints 1 to 14
(OUT endpoints only)
12h to 1Fh
isochronous: N
1023 bytes
interrupt or bulk:
N
≤ 64 bytes
Stall Control OUT Endpoint
endpoint 0 OUT
40h
-
Stall Control IN Endpoint
endpoint 0 IN
41h
-
Stall Endpoint n (n = 1 to 14)
endpoints 1 to 14
42h to 4Fh
-
Read Control OUT Status
Endpoint Status register
endpoint 0 OUT
50h
read 1 byte
Read Control IN Status
Endpoint Status register
endpoint 0 IN
51h
read 1 byte
Read Endpoint n Status (n =
1 to 14)
Endpoint Status register n
endpoints 1 to 14
52h to 5Fh
read 1 byte
Validate Control OUT Buffer
illegal: IN endpoints only[1] (60h)
-
Validate Control IN Buffer
FIFO endpoint 0 IN
61h
-
Validate Endpoint n Buffer (n =
1 to 14)
FIFO endpoints 1 to 14 (IN
endpoints only)[1]
62h to 6Fh
-
Clear Control OUT Buffer
FIFO endpoint 0 OUT
70h
-
Clear Control IN Buffer
illegal[2]
(71h)
-
Clear Endpoint n Buffer (n =
1 to 14)
FIFO endpoints 1 to 14
(OUT endpoints only)[2]
72h to 7Fh
-
Unstall Control OUT Endpoint
endpoint 0 OUT
80h
-
Unstall Control IN Endpoint
endpoint 0 IN
81h
-
Unstall Endpoint n (n = 1 to 14) endpoints 1 to 14
82h to 8Fh
-
Check Control OUT Status[3]
Endpoint Status Image
register endpoint 0 OUT
D0h
read 1 byte
Check Control IN Status[3]
Endpoint Status Image
register endpoint 0 IN
D1h
read 1 byte
Check Endpoint n Status (n =
1 to 14)[3]
Endpoint Status Image
register n endpoints
1to14
D2h to DFh read 1 byte
Acknowledge Setup
endpoint 0 IN and OUT
F4h
-
Table 13.
Command and register overview …continued
Name
Destination
Code
Transaction
Reference
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