參數(shù)資料
型號: ISP1183BS,157
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC32
封裝: 5 X 5 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-617-1, HVQFN-32
文件頁數(shù): 29/65頁
文件大?。?/td> 306K
代理商: ISP1183BS,157
ISP1183_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 7 June 2007
35 of 65
NXP Semiconductors
ISP1183
Low-power USB Peripheral Controller with DMA
12.2.7 Acknowledge Setup (F4h)
This command acknowledges to the host that a SETUP packet was received. The arrival
of a SETUP packet disables the Validate Buffer and Clear Buffer commands for the control
IN and OUT endpoints. The microcontroller needs to re-enable these commands by
sending an Acknowledge Setup command, see Section 9.5.
Code: F4h — acknowledge setup
Transaction — none
12.3 DMA commands
12.3.1 DMA Function and Scratch register (R/W: B3h/B2h)
This command accesses the 16-bit DMA Function and Scratch register, which can be
used by rmware to save and restore information. For example, the device status before
powering down in the suspend state. The register bit allocation is given in Table 30.
Code: B2h/B3h — write or read DMA Function and Scratch register
Transaction — write or read 2 bytes
2
SETUPT
Logic 1 indicates that the buffer contains a set-up packet.
1
CPUBUF
This bit indicates which buffer is currently selected for CPU access (0 =
primary buffer, 1 = secondary buffer).
0
-
reserved
Table 29.
Endpoint Status Image register: bit description …continued
Bit
Symbol
Description
Table 30.
DMA Function and Scratch register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
DMAEN
reserved
SFIRH[4:0]
Reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
SFIRL[7:0]
Reset
00000000
Access
R/W
Table 31.
DMA Function and Scratch register: bit description
Bit
Symbol
Description
15
DMAEN
Writing logic 1 enables DMA function.
14 to 13
-
reserved; must be logic 0
12 to 8
SFIRH[4:0]
Scratch Information register (high byte)
7 to 0
SFIRL[7:0]
Scratch Information register (low byte)
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