參數(shù)資料
型號: ISP1181BBS,518
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC48
封裝: 7 X 7 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-619-2, HVQFN-48
文件頁數(shù): 37/71頁
文件大?。?/td> 351K
代理商: ISP1181BBS,518
Philips Semiconductors
ISP1181B
Full-speed USB peripheral controller
Product data
Rev. 02 — 07 December 2004
41 of 70
9397 750 13958
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
13. Interrupts
Figure 8 shows the interrupt logic of the ISP1181B. Each of the indicated USB events
is logged in a status bit of the Interrupt Register. Corresponding bits in the Interrupt
Enable Register determine whether or not an event will generate an interrupt.
Interrupts can be masked globally by means of the INTENA bit of the Mode Register
The active level and signalling mode of the INT output is controlled by the INTPOL
and INTLVL bits of the Hardware Conguration Register (see Table 21). Default
settings after reset are active LOW and level mode. When pulse mode is selected, a
pulse of 166 ns is generated when the OR-ed combination of all interrupt bits
changes from logic 0 to logic 1.
8
EP0OUT
A logic 1 indicates the interrupt source: control OUT endpoint.
7
BUSTATUS
It monitors the current USB bus status (0 = awake,
1 = suspend).
6
SP_EOT
A logic 1 indicates that an EOT interrupt has occurred for a short
packet.
5
PSOF
A logic 1 indicates that an interrupt is issued every 1 ms
because of the Pseudo SOF; after 3 missed SOFs ‘suspend’
state is entered.
4
SOF
A logic 1 indicates that a SOF condition was detected.
3
EOT
A logic 1 indicates that an internal EOT condition was generated
by the DMA Counter reaching zero.
2
SUSPND
A logic 1 indicates that an ‘a(chǎn)wake’ to ‘suspend’ change of state
was detected on the USB bus.
1
RESUME
A logic 1 indicates that a ‘resume’ state was detected.
0
RESET
A logic 1 indicates that a bus reset condition was detected.
Table 49:
Interrupt Register: bit description…continued
Bit
Symbol
Description
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