參數(shù)資料
型號(hào): ISP1181BBS,518
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC48
封裝: 7 X 7 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-619-2, HVQFN-48
文件頁(yè)數(shù): 2/71頁(yè)
文件大小: 351K
代理商: ISP1181BBS,518
Philips Semiconductors
ISP1181B
Full-speed USB peripheral controller
Product data
Rev. 02 — 07 December 2004
9 of 70
9397 750 13958
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
7.
Functional description
The ISP1181B is a full-speed USB peripheral controller with up to 14 congurable
endpoints. It has a fast general-purpose parallel interface for communication with
many types of microcontrollers or microprocessors. It supports different bus
congurations (see Table 3) and local DMA transfers of up to 16 bytes per cycle. The
block diagram is given in Figure 1.
The ISP1181B has 2462 bytes of internal FIFO memory, which is shared among the
enabled USB endpoints. The type and FIFO size of each endpoint can be individually
congured, depending on the required packet size. Isochronous and bulk endpoints
are double-buffered for increased data throughput.
The ISP1181B requires a single supply voltage of 3.3 V or 5.0 V and has an internal
3.3 V voltage regulator for powering the analog USB transceiver. It supports
bus-powered operation.
The ISP1181B operates on a 6 MHz oscillator frequency. A programmable clock
output is available up to 48 MHz. During ‘suspend’ state the 100 kHz
± 50 %
LazyClock frequency can be output.
7.1 Analog transceiver
The transceiver is compliant with the
Universal Serial Bus Specication Rev. 2.0 (full
speed). It interfaces directly with the USB cable through external termination
resistors.
7.2 Philips Serial Interface Engine (SIE)
The Philips SIE implements the full USB protocol layer. It is completely hardwired for
speed and needs no rmware intervention. The functions of this block include:
synchronization pattern recognition, parallel/serial conversion, bit (de-)stufng, CRC
checking/generation, Packet IDentier (PID) verication/generation, address
recognition, handshake evaluation/generation.
7.3 Memory Management Unit (MMU) and integrated RAM
The MMU and the integrated RAM provide the conversion between the USB speed
(12 Mbit/s bursts) and the parallel interface to the microcontroller (max. 12 Mbyte/s).
This allows the microcontroller to read and write USB packets at its own speed.
7.4 SoftConnect
The connection to the USB is accomplished by bringing D
+ (for full-speed USB
peripherals) HIGH through a 1.5 k
pull-up resistor. In the ISP1181B, the 1.5 k
pull-up resistor is integrated on-chip and is not connected to VCC by default. The
connection is established by a command sent from the external/system
microcontroller. This allows the system microcontroller to complete its initialization
sequence before deciding to establish connection with the USB. Reinitialization of the
USB connection can also be performed without disconnecting the cable.
The ISP1181B will check for USB VBUS availability before the connection can be
established. VBUS sensing is provided through pin VBUS.
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