參數(shù)資料
型號: ISP1181BBS,518
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC48
封裝: 7 X 7 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-619-2, HVQFN-48
文件頁數(shù): 25/71頁
文件大小: 351K
代理商: ISP1181BBS,518
Philips Semiconductors
ISP1181B
Full-speed USB peripheral controller
Product data
Rev. 02 — 07 December 2004
30 of 70
9397 750 13958
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
12.1.6
Write/Read DMA Conguration
This command denes the DMA conguration of ISP1181B and enables/disables
DMA transfers. The command accesses the DMA Conguration Register, which
consists of 2 bytes. The bit allocation is given in Table 24. A bus reset will clear bit
DMAEN (DMA disabled), all other bits remain unchanged.
Code (Hex): F0/F1 — write/read DMA Conguration
Transaction — write/read 2 bytes
[1]
Unchanged by a bus reset.
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
SP_IEEOT
IEPSOF
IESOF
IEEOT
IESUSP
IERESM
IERST
Reset
00000000
Access
R/W
Table 23:
Interrupt Enable Register: bit description
Bit
Symbol
Description
31 to 24
-
reserved; must write logic 0
23 to 10
IEP14 to IEP1
A logic 1 enables interrupts from the indicated endpoint.
9
IEP0IN
A logic 1 enables interrupts from the control IN endpoint.
8
IEP0OUT
A logic 1 enables interrupts from the control OUT endpoint.
7
-
reserved
6
SP_IEEOT
A logic 1 enables interrupt upon detection of a short packet.
5
IEPSOF
A logic 1 enables 1 ms interrupts upon detection of
Pseudo SOF.
4
IESOF
A logic 1 enables interrupt upon SOF detection.
3
IEEOT
A logic 1 enables interrupt upon EOT detection.
2
IESUSP
A logic 1 enables interrupt upon detection of ‘suspend’ state.
1
IERESM
A logic 1 enables interrupt upon detection of a ‘resume’ state.
0
IERST
A logic 1 enables interrupt upon detection of a bus reset.
Table 24:
DMA Conguration Register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
CNTREN
SHORTP
reserved
Reset
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
EPDIX[3:0]
DMAEN
reserved
BURSTL[1:0]
Reset
00
Access
R/W
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