參數(shù)資料
型號(hào)： ISP1181BBS,518
廠商： ST-ERICSSON
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQCC48
封裝： 7 X 7 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-619-2, HVQFN-48
文件頁(yè)數(shù)： 29/71頁(yè)
文件大?。?/td> 351K
代理商： ISP1181BBS,518
Philips Semiconductors
ISP1181B
Full-speed USB peripheral controller
Product data
Rev. 02 — 07 December 2004
34 of 70
9397 750 13958
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Transaction — read 1 byte
12.2.3
Stall Endpoint/Unstall Endpoint
These commands are used to stall or unstall an endpoint. The commands modify the
content of the Endpoint Status Register (see Table 31).
A stalled control endpoint is automatically unstalled when it receives a SETUP token,
regardless of the packet content. If the endpoint should stay in its stalled state, the
microcontroller can restall it with the Stall Endpoint command.
When a stalled endpoint is unstalled (either by the Unstall Endpoint command or by
receiving a SETUP token), it is also reinitialized. This ushes the buffer: if it is an OUT
buffer it waits for a DATA 0 PID, if it is an IN buffer it writes a DATA 0 PID.
Code (Hex): 40 to 4F — stall (control OUT, control IN, endpoint 1 to 14)
Code (Hex): 80 to 8F — unstall (control OUT, control IN, endpoint 1 to 14)
Transaction — none
Table 31:
Endpoint Status Register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
EPSTAL
EPFULL1
EPFULL0
DATA_PID
OVER
WRITE
SETUPT
CPUBUF
reserved
Reset
00000000
Access
RRRRRRRR
Table 32:
Endpoint Status Register: bit description
Bit
Symbol
Description
7
EPSTAL
This bit indicates whether the endpoint is stalled or not
(1 = stalled, 0 = not stalled).
Set to logic 1 by a Stall Endpoint command, cleared to logic 0 by
an Unstall Endpoint command. The endpoint is automatically
unstalled upon reception of a SETUP token.
6
EPFULL1
A logic 1 indicates that the secondary endpoint buffer is full.
5
EPFULL0
A logic 1 indicates that the primary endpoint buffer is full.
4
DATA_PID
This bit indicates the data PID of the next packet (0 = DATA PID,
1 = DATA1 PID).
3
OVERWRITE
This bit is set by hardware, a logic 1 indicating that a new Setup
packet has overwritten the previous setup information, before it
was acknowledged or before the endpoint was stalled. This bit is
cleared by reading, if writing the setup data has nished.
Firmware must check this bit before sending an Acknowledge
Setup command or stalling the endpoint. Upon reading a logic 1
the rmware must stop ongoing setup actions and wait for a new
Setup packet.
2
SETUPT
A logic 1 indicates that the buffer contains a Setup packet.
1
CPUBUF
This bit indicates which buffer is currently selected for CPU
access (0 = primary buffer, 1 = secondary buffer).
0
-
reserved
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