參數(shù)資料
型號(hào): ISP1181BBS,518
廠(chǎng)商: ST-ERICSSON
元件分類(lèi): 總線(xiàn)控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC48
封裝: 7 X 7 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-619-2, HVQFN-48
文件頁(yè)數(shù): 26/71頁(yè)
文件大小: 351K
代理商: ISP1181BBS,518
Philips Semiconductors
ISP1181B
Full-speed USB peripheral controller
Product data
Rev. 02 — 07 December 2004
31 of 70
9397 750 13958
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
12.1.7
Write/Read DMA Counter
This command accesses the DMA Counter Register, which consists of 2 bytes. The
bit allocation is given in Table 26. Writing to the register sets the number of bytes for a
DMA transfer. Reading the register returns the number of remaining bytes in the
current transfer. A bus reset will not change the programmed bit values.
The internal DMA counter is automatically reloaded from the DMA Counter Register
when DMA is re-enabled (DMAEN = 1). See Section 12.1.6 for more details.
Code (Hex): F2/F3 — write/read DMA Counter Register
Transaction — write/read 2 bytes
Table 25:
DMA Conguration Register: bit description
Bit
Symbol
Description
15
CNTREN
A logic 1 enables the generation of an EOT condition, when the
DMA Counter Register reaches zero. Bus reset value:
unchanged.
14
SHORTP
A logic 1 enables short/empty packet mode. When receiving
(OUT endpoint) a short/empty packet an EOT condition is
generated. When transmitting (IN endpoint) this bit should be
cleared. Bus reset value: unchanged.
13 to 8
-
reserved
7 to 4
EPDIX[3:0]
Indicates the destination endpoint for DMA, see Table 7.
3
DMAEN
Writing a logic 1 enables DMA transfer, a logic 0 forces the end
of an ongoing DMA transfer. Reading this bit indicates whether
DMA is enabled (0 = DMA stopped, 1 = DMA enabled). This bit
is cleared by a bus reset.
2
-
reserved
1 to 0
BURSTL[1:0]
Selects the DMA burst length:
00 — single-cycle mode (1 byte)
01 — burst mode (4 bytes)
10 — burst mode (8 bytes)
11 — burst mode (16 bytes).
Bus reset value: unchanged.
Table 26:
DMA Counter Register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
DMACRH[7:0]
Reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
DMACRL[7:0]
Reset
00000000
Access
R/W
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