參數(shù)資料
型號: ISP1181BBS,518
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC48
封裝: 7 X 7 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-619-2, HVQFN-48
文件頁數(shù): 3/71頁
文件大?。?/td> 351K
代理商: ISP1181BBS,518
Philips Semiconductors
ISP1181B
Full-speed USB peripheral controller
Product data
Rev. 02 — 07 December 2004
10 of 70
9397 750 13958
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
VBUS sensing prevents the peripheral from wake-up when VBUS is not present.
Without VBUS sensing, any activity or noise on (D+, D-) might wake up the peripheral.
With VBUS sensing, (D+, D-) is decoupled when no VBUS is present. Therefore, even if
there is noise on the (D+, D-) lines, it is not taken into account. This ensures that the
peripheral remains in the suspend state.
Remark: Note that the tolerance of the internal resistors is 25 %. This is higher than
the 5 % tolerance specied by the USB specication. However, the overall voltage
specication for the connection can still be met with a good margin. The decision to
make use of this feature lies with the USB equipment designer.
7.5 GoodLink
Indication of a good USB connection is provided at pin GL through GoodLink
technology. During enumeration, the LED indicator will blink on momentarily. When
the ISP1181B has been successfully enumerated (the peripheral address is set), the
LED indicator will remain permanently on. Upon each successful packet transfer (with
ACK) to and from the ISP1181B, the LED will blink off for 100 ms. During ‘suspend’
state, the LED will remain off.
This feature provides a user-friendly indication of the status of the USB peripheral,
the connected hub, and the USB trafc. It is a useful eld diagnostics tool for isolating
faulty equipment. It can therefore help to reduce eld support and hotline overhead.
7.6 Bit clock recovery
The bit clock recovery circuit recovers the clock from the incoming USB data stream
using a 4 times over-sampling principle. It is able to track jitter and frequency drift as
specied by the
USB Specication Rev. 2.0.
7.7 Voltage regulator
A 5 V-to-3.3 V voltage regulator is integrated on-chip to supply the analog transceiver
and internal logic. This voltage is available at pin Vreg(3.3) to supply an external 1.5 k
pull-up resistor on the D
+ line. Alternatively, the ISP1181B provides SoftConnect
technology via an integrated 1.5 k
pull-up resistor (see Section 7.4).
7.8 PLL clock multiplier
A 6 MHz to 48 MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip.
This allows for the use of a low-cost 6 MHz crystal, which also minimizes EMI. No
external components are required for the operation of the PLL.
7.9 Parallel I/O (PIO) and Direct Memory Access (DMA) interface
A generic PIO interface is dened for speed and ease-of-use. It also allows direct
interfacing to most microcontrollers. To a microcontroller, the ISP1181B appears as a
memory device with an 8/16-bit data bus and a 1-bit address line. The ISP1181B
supports both multiplexed and non-multiplexed address and data buses.
The ISP1181B can also be congured as a DMA slave device to allow more efcient
data transfer. One of the 14 endpoint FIFOs may directly transfer data to/from the
local shared memory. The DMA interface can be congured independently from the
PIO interface.
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