參數(shù)資料
型號(hào)： ISP1181BBS,518
廠商： ST-ERICSSON
元件分類(lèi)： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQCC48
封裝： 7 X 7 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-619-2, HVQFN-48
文件頁(yè)數(shù)： 27/71頁(yè)
文件大?。?/td> 351K
代理商： ISP1181BBS,518
Philips Semiconductors
ISP1181B
Full-speed USB peripheral controller
Product data
Rev. 02 — 07 December 2004
32 of 70
9397 750 13958
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
12.1.8
Reset Device
This command resets the ISP1181B in the same way as an external hardware reset
via input RESET. All registers are initialized to their ‘reset’ values.
Code (Hex): F6 — reset the device
Transaction — none
12.2 Data ow commands
Data ow commands are used to manage the data transmission between the USB
endpoints and the system microcontroller. Much of the data ow is initiated via an
interrupt to the microcontroller. The data ow commands are used to access the
endpoints and determine whether the endpoint FIFOs contain valid data.
Remark: The IN buffer of an endpoint contains input data for the host, the OUT buffer
receives output data from the host.
12.2.1
Write/Read Endpoint Buffer
This command is used to access endpoint FIFO buffers for reading or writing. First,
the buffer pointer is reset to the beginning of the buffer. Following the command, a
maximum of (N
+ 2) bytes can be written or read, N representing the size of the
endpoint buffer. For 16-bit access the maximum number of words is (M + 1), with M
given by (N
+ 1) DIV 2. After each read/write action the buffer pointer is automatically
incremented by 1 (8-bit bus width) or by 2 (16-bit bus width).
In DMA access the rst 2 bytes or the rst word (the packet length) are skipped:
transfers start at the third byte or the second word of the endpoint buffer. When
reading, the ISP1181B can detect the last byte/word via the EOP condition. When
writing to a bulk/interrupt endpoint, the endpoint buffer must be completely lled
before sending the data to the host. Exception: when a DMA transfer is stopped by an
external EOT condition, the current buffer content (full or not) is sent to the host.
Remark: Reading data after a Write Endpoint Buffer command or writing data after a
Read Endpoint Buffer command data will cause unpredictable behavior of ISP1181B.
Code (Hex): 01 to 0F — write (control IN, endpoint 1 to 14)
Code (Hex): 10, 12 to 1F — read (control OUT, endpoint 1 to 14)
Transaction — write/read maximum (N
+ 2) bytes (isochronous endpoint: N ≤ 1023,
bulk/interrupt endpoint: N
≤ 32)
The data in the endpoint FIFO must be organized as shown in Table 28. Examples of
endpoint FIFO access are given in Table 29 (8-bit bus) and Table 30 (16-bit bus).
Table 27:
DMA Counter Register: bit description
Bit
Symbol
Description
15 to 8
DMACRH[7:0] DMA Counter Register (high byte)
7 to 0
DMACRL[7:0]
DMA Counter Register (low byte)
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