Table 98. MANAGEMENT DATA INTERFACE PINS PIN# NAME TYPE DESCRIPTION P11 MDIO I/O (open drain output) Management Address/Data I/O. 1.2V CMOS inp" />
參數(shù)資料
型號(hào)： ISL35822LPIK
廠商： Intersil
文件頁數(shù)： 52/75頁
文件大?。?/td> 0K
描述： IC CLOCK/DATA RECOVERY 192EBGA-B
標(biāo)準(zhǔn)包裝： 90
類型： 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器
PLL： 無
輸入： CML
輸出： CML，CMOS
電路數(shù)： 1
比率 - 輸入:輸出： 8:8
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.59Gbps
電源電壓： 1.3 V ~ 1.41 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 192-EBGA
供應(yīng)商設(shè)備封裝： 192-EBGA-B（17x17）
包裝： 托盤
56
Table 98. MANAGEMENT DATA INTERFACE PINS
PIN#
NAME
TYPE
DESCRIPTION
P11
MDIO
I/O (open drain output)
Management Address/Data I/O. 1.2V CMOS input, 2.5V Tolerant
R11
MDC
Input
Management Interface Clock. 1.2V CMOS, 2.5V Tolerant, with Schmitt trigger
R12
PADR[4]
Input
Management Port Address Setting 1.2V CMOS
T12
PADR[3]
P12
PADR[2]
N12
PADR[1]
T11
PADR[0]
Table 99. MISCELLANEOUS PINS
PIN#
NAME
TYPE
DESCRIPTION
N11
MF[0]
Output
1.5V CMOS
Multi-function Outputs, Lanes 0 - 3. The functions of these pins are enabled via the MDIO
Interface.
The default condition for these pins is PHY XGXS BIST_ERR. See Table 81 (bits MF_SEL
and MF_CTRL) for further details.
P10
MF[1]
B9
MF[2]
A10
MF[3]
N10
RSTN
Input
Chip Reset (FIFO Clear) Assert RSTN for at least 10s from power up. Active low. Schmitt
trigger input, 1.2V CMOS, 2.5V tolerant.
D10
BIST_ENA
Input (with pulldown) Built-In Self Test Enable- Active High. When high, enables internal 223-1 byte PRBS test
function generator and checker. 1.5V CMOS
A11
LX4_MODE
Input (with pulldown) CX4/LX4 Mode Select. When high, LX4 mode is selected. When low, CX4 mode is
selected. This pin decides the trigger sources of LASI, and the default pre-emphasis and
equalization strength of the high speed serial port on the PMA/PMD side. 1.5V CMOS
B11
LASI
Output (open drain) Link Alarm Status Interrupt Request. When low, pin indicates the existence of an incorrect
condition. An external 10-22k
pull-up to 1.2V or 1.5V is recommended. 1.2V CMOS, 2.5V
tolerant.
D7
OPTXLBC (1)
Input
TX Laser Bias Current. Optical monitoring input. Active level is latched into register bit
1.36868.9 and can be configured to trigger LASI. When this pin is not driven by an external
device, it should be pulled inactive (default down). 1.5V CMOS, 2.5V tolerant.
D5
OPTTEMP(1)
Input
Transceiver Temperature. Optical monitoring input. Active level is latched into register bit
1.36868.8 and can be configured to trigger LASI. When this pin is not driven by an external
device, it should be pulled inactive (default down). 1.5V CMOS, 2.5V tolerant.
D6
OPTXLOP(1)
Input
TX Laser Output Power. Optical monitoring input. Active level is latched into register bit
1.36868.7 and can be configured to trigger LASI. When this pin is not driven by an external
device, it should be pulled inactive (default down). 1.5V CMOS, 2.5V tolerant.
N8
TX_FAULT(2)
Input
TX Fault Condition. Transmitter (Egress) external fault input. Active level is latched into
register bits 1.10 and 1.36868.6 and can be configured to trigger LASI. When this pin is not
driven by an external device, it should be pulled inactive (default down). 1.5V CMOS, 2.5V
tolerant.
C5
OPRXOP(1)
Input
Receive Optical Power. Optical monitoring input 4. Active level is latched into register bit
1.36867.5 and can be configured to trigger LASI. When this pin is not driven by an external
device, it should be pulled inactive (default down). 1.5V CMOS, 2.5V tolerant.
A6
OPRLOS[3] (1) Input
Optical Receiver Loss Of Signal. Optical monitoring input 5 – 8. Active (loss) levels are
latched into register 1.10 and can be configured to trigger LASI. When these pins are not
driven by an external device, they should pulled inactive (default down). 1.5V CMOS, 2.5V
tolerant.
A5
OPRLOS[2] (1)
A7
OPRLOS[1] (1)
B7
OPRLOS[0] (1)
D11
XP_ENA
Input
XENPAK Enable. Enable XENPAK support. Active high. Activates 2-wire serial bus
interface. 1.5V CMOS, 2.5V tolerant.
ISL35822
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